[coreboot-gerrit] Change in coreboot[master]: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22947 )

Change subject: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.
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Patch Set 1:

(4 comments)

https://review.coreboot.org/#/c/22947/1//COMMIT_MSG
Commit Message:

https://review.coreboot.org/#/c/22947/1//COMMIT_MSG@7
PS1, Line 7: soc/intel
soc/intel/skylake


https://review.coreboot.org/#/c/22947/1//COMMIT_MSG@14
PS1, Line 14: CL:22629,CL:22899
What CLs are these? I was not able to find anything relevant.


https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip.h
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip.h@202
PS1, Line 202: u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS];
Can you please add a comment indicating what this config option does and what values it can be set to?


https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip_fsp20.c
File src/soc/intel/skylake/chip_fsp20.c:

https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip_fsp20.c@174
PS1, Line 174: 0x1F
What does this value mean? Can you please add a comment?



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Gerrit-Change-Number: 22947
Gerrit-PatchSet: 1
Gerrit-Owner: Divya Chellappa <divya.chellappa at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Comment-Date: Tue, 19 Dec 2017 15:13:06 +0000
Gerrit-HasComments: Yes
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