[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add tsc_freq.c to verstage

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19094 )

Change subject: soc/intel/skylake: Add tsc_freq.c to verstage
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soc/intel/skylake: Add tsc_freq.c to verstage

This is required to provide tsc freq required by timer library.

BUG=b:35583330
TEST=Verified that delay(5) in verstage adds a delay of 5 seconds.

Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
Reviewed-on: https://review.coreboot.org/19094
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
M src/soc/intel/skylake/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified



diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f7b4971..f9c267e 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -33,6 +33,7 @@
 verstage-y += pmutil.c
 verstage-y += bootblock/i2c.c
 verstage-y += spi.c
+verstage-y += tsc_freq.c
 
 romstage-y += flash_controller.c
 romstage-y += gpio.c

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)