[coreboot-gerrit] Change in coreboot[master]: Sky Lake/Kaby Lake mainboards: Enable early init for SPI Flash

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19096 )

Change subject: Sky Lake/Kaby Lake mainboards: Enable early init for SPI Flash
......................................................................

Sky Lake/Kaby Lake mainboards: Enable early init for SPI Flash

Now that we have an explicit option for performing early init for SPI
buses, enable early init for SPI flash bus for all skylake and
kabylake mainboards.

BUG=b:35583330

Change-Id: I9913eac6d19ebf8afbb4e8307f017e9b44fa2753
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/mainboard/google/chell/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/lars/devicetree.cb
M src/mainboard/google/poppy/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
9 files changed, 26 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19096/1

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 477a8aa..678308f 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -165,6 +165,9 @@
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index d8f6362..e329333 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -192,6 +192,9 @@
 		.fall_time_ns = 30,
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index e498dc9..1119ed2 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -170,6 +170,9 @@
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	register "speed_shift_enable" = "1"
 	register "tdp_pl2_override" = "7"
 	register "tcc_offset" = "10"     # TCC of 90C
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index f7a2e52..1bb46d5 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -180,6 +180,9 @@
 		[PchSerialIoIndexUart2] = PchSerialIoPci,
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# PL2 override 15W
 	register "tdp_pl2_override" = "15"
 
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index b95ecf5..9f4b604 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -177,6 +177,9 @@
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# PL2 override 25W
 	register "tdp_pl2_override" = "25"
 
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index 7bf28d0..f3a66cb 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -157,6 +157,8 @@
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"		# Camera
 	register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"		# Audio
 
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index 00b20ba..4d44add 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -193,6 +193,9 @@
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
index 3696292..1ab60e8 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
@@ -190,6 +190,9 @@
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 11cb31a..ac02ac5 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -181,6 +181,9 @@
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
+	# SPI Flash
+	register "spi[SKYLAKE_FAST_SPI_BUS].early_init" = "1"
+
 	# PL2 override 25W
 	register "tdp_pl2_override" = "25"
 

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I9913eac6d19ebf8afbb4e8307f017e9b44fa2753
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>