[coreboot-gerrit] Patch merged into coreboot/master: acpi_device: Add support for writing ACPI I2C descriptors

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1010b4aeacd709500e31ec10d96187f8835a4f2d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon May 9 20:10:47 2016 -0700

    acpi_device: Add support for writing ACPI I2C descriptors
    
    Add required definitions to describe an ACPI I2C bus and a method to
    write the I2cSerialBus() descriptor to the SSDT.
    
    This will be used by device drivers to describe their I2C resources to
    the OS.  The devicetree i2c device can supply the address and 7 or 10
    bit mode as well as indicate the GPIO controller device, and the bus
    speed can be fixed or configured by the driver.
    
    chip.h:
      struct drivers_i2c_generic_config {
        enum i2c_speed bus_speed;
      };
    
    generic.c:
      void acpi_fill_ssdt_generator(struct device *dev) {
        struct drivers_i2c_generic_config *config = dev->chip_info;
        struct acpi_i2c i2c = {
          .address = dev->path->i2c.device,
          .mode_10bit = dev->path.i2c.mode_10bit,
          .speed = config->bus_speed ? : I2C_SPEED_FAST,
          .resource = acpi_device_path(dev->bus->dev)
        };
        ...
        acpi_device_write_i2c(&i2c);
        ...
      }
    
    devicetree.cb:
      device pci 15.0 on
        chip drivers/i2c/generic
          device i2c 10.0 on end
        end
      end
    
    SSDT.dsl:
      I2cSerialBus (0x10, ControllerInitiated, 400000, AddressingMode7Bit,
                    "\\_SB.PCI0.I2C0", 0, ResourceConsumer)
    
    Change-Id: I598401ac81a92c72f19da0271af1e218580a6c49
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/14935
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/14935 for details.

-gerrit