[coreboot-gerrit] Patch merged into coreboot/master: acpi_device: Add support for writing ACPI GPIO descriptors

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit cfb6ea7e659be66c90a94841a33e69afa8163eab
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon May 9 17:08:38 2016 -0700

    acpi_device: Add support for writing ACPI GPIO descriptors
    
    Add definitions to describe GPIOs in generated ACPI objects and a
    method to write a GpioIo() or GpioInt() descriptor to the SSDT.
    
    ACPI GPIOs have many possible configuration options and a structure
    is created to describe it accurately in ACPI terms.  There are many
    shared descriptor fields between GpioIo() and GpioInt() so the same
    function can write both types.
    
    GpioInt shares many properties with ACPI Interrupts and the same types
    are re-used here where possible.  One addition is that GpioInt can be
    configured to trigger on both low and high edge transitions.
    
    One descriptor can describe multiple GPIO pins (limited to 8 in this
    implementation) that all share configuration and controller and are
    used by the same device scope.
    
    Accurately referring to the GPIO controller that this pin is connected
    to requires the SoC/board to implement a function handler for
    acpi_gpio_path(), or for the caller to provide this directly as a
    string in the acpi_gpio->reference variable.
    
    This will get used by device drivers to describe their resources in
    the SSDT.  Here is a sample for a Maxim 98357A I2S codec which has a
    GPIO for power and channel selection called "sdmode".
    
    chip.h:
      struct drivers_generic_max98357a_config {
        struct acpi_gpio sdmode_gpio;
      };
    
    max98357a.c:
      void acpi_fill_ssdt_generator(struct device *dev) {
        struct drivers_generic_max98357a_config *config = dev->chip_info;
        ...
        acpi_device_write_gpio(&config->sdmode_gpio);
        ...
      }
    
    devicetree.cb:
      device pci 1f.3 on
        chip drivers/generic/max98357a
          register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C5)"
          device generic 0 on end
        end
      end
    
    SSDT.dsl:
      GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
              "\\_SB.PCI0.GPIO", 0, ResourceConsumer, ,) { 53 }
    
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Change-Id: Ibf5bab9c4bf6f21252373fb013e78f872550b167
    Reviewed-on: https://review.coreboot.org/14934
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/14934 for details.

-gerrit