[coreboot-gerrit] Patch merged into coreboot/master: acpi_device: Add support for writing ACPI SPI descriptors

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 70c86d9b265a7ea821fcd1b0684d60393d9908c1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue May 10 07:26:34 2016 -0700

    acpi_device: Add support for writing ACPI SPI descriptors
    
    Add required definitions to describe an ACPI SPI bus and a method to
    write the SpiSerialBus() descriptor to the SSDT.
    
    This will be used by device drivers to describe their SPI resources to
    the OS.  SPI devices are not currently enumerated in the devicetree but
    can be enumerated by device drivers directly.
    
    generic.c:
      void acpi_fill_ssdt_generator(struct device *dev) {
        struct acpi_spi spi = {
          .device_select = dev->path->generic.device.id,
          .device_select_polarity = SPI_POLARITY_LOW,
          .spi_wire_mode = SPI_4_WIRE_MODE,
          .speed = 1000 * 1000; /* 1 mHz */
          .data_bit_length = 8,
          .clock_phase = SPI_CLOCK_PHASE_FIRST,
          .clock_polarity = SPI_POLARITY_LOW,
          .resource = acpi_device_path(dev->bus->dev)
        };
        ...
        acpi_device_write_spi(&spi);
        ...
      }
    
    devicetree.cb:
      device pci 1e.2 on
        chip drivers/spi/generic
          device generic 0 on end
        end
      end
    
    SSDT.dsl:
      SpiSerialBus (0, PolarityLow, FourWireMode, 8, ControllerInitiated,
                    1000000, ClockPolarityLow, ClockPhaseFirst,
                    "\\_SB.PCI0.SPI0", 0, ResourceConsumer)
    
    Change-Id: I0ef83dc111ac6c19d68872ab64e1e5e3a7756cae
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/14936
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/14936 for details.

-gerrit