[coreboot-gerrit] New patch to review for coreboot: DO NOT MERGE: More SPI flash cache testing

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14876

-gerrit

commit b7852ca46ce151013a4ac6b1dacd8ea98500864a
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu May 12 07:22:05 2016 -0700

    DO NOT MERGE: More SPI flash cache testing
    
    Change-Id: I3be786847de97123c681ecfa47a9653513f0a6cd
---
 src/mainboard/intel/galileo/Kconfig     |  1 +
 src/soc/intel/quark/romstage/romstage.c | 57 ++++++++++++++++++++++++++++-----
 2 files changed, 50 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index 968976d..85be611 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select ADD_FSP_PDAT_FILE
 	select ADD_FSP_RAW_BIN
+#	select HAVE_FSP_BIN
 	select ADD_RMU_FILE
 	select BOARD_ROMSIZE_KB_8192
 	select DEBUG_BOOT_STATE
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 7291d97..de1a767 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -48,6 +48,35 @@ static const struct reg_script i2c_gpio_controller_init[] = {
 
 void car_soc_pre_console_init(void)
 {
+#if 1
+	union {
+		uint32_t u32[2];
+		msr_t msr;
+	} address;
+	union {
+		uint32_t u32[2];
+		msr_t msr;
+	} mask;
+	uint32_t size;
+
+	mask.u32[1] = (1 << ((cpuid_eax(0x80000008) - 32 ) & 0xff)) - 1;
+	address.u32[1] = 0;
+
+	/* Cache the SPI flash */
+	size = 8 * 1024 * 1024;
+	address.u32[0] = (0 - size) | MTRR_TYPE_WRBACK;
+	mask.u32[0] = (~(size - 1)) | MTRR_PHYS_MASK_VALID;
+	soc_mtrr_write(MTRR_PHYS_BASE(0), address.msr);
+	soc_mtrr_write(MTRR_PHYS_MASK(0), mask.msr);
+
+	/* Cache the ESRAM */
+	size = 512 * 1024;
+	address.u32[0] = 0x80000000 | MTRR_TYPE_WRBACK;
+	mask.u32[0] = (~(size - 1)) | MTRR_PHYS_MASK_VALID;
+	soc_mtrr_write(MTRR_PHYS_BASE(1), address.msr);
+	soc_mtrr_write(MTRR_PHYS_MASK(1), mask.msr);
+#endif
+
 	if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
 		set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
 			UART_BASE_ADDRESS);
@@ -55,16 +84,11 @@ void car_soc_pre_console_init(void)
 
 void car_soc_post_console_init(void)
 {
-	union {
-		uint32_t u32[2];
-		msr_t msr;
-	} value;
+legacy_gpio_pin_value(0, 0);
 
-	value.u32[0] = ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRBACK;
-	value.u32[1] = ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID;
-	soc_mtrr_write(MTRR_PHYS_BASE(0), value.msr);
-	value.msr = soc_mtrr_read(MTRR_PHYS_BASE(0));
+	report_platform_info();
 
+/* Display the MTRRs */
 soc_display_mtrrs();
 
 	report_platform_info();
@@ -86,6 +110,23 @@ struct chipset_power_state *fill_power_state(void)
 	return ps;
 }
 
+void gpio_test(void);
+#include <timestamp.h>
+
+void gpio_test(void)
+{
+	/* Initialize timestamp book keeping only once. */
+	timestamp_init(0);
+
+	/* Call into pre-console init code then initialize console. */
+	car_soc_pre_console_init();
+	car_mainboard_pre_console_init();
+	console_init();
+
+	/* Test the GPIOs */
+	legacy_gpio_pin_value(0, 0);
+}
+
 /* Initialize the UPD parameters for MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd)