[coreboot-gerrit] New patch to review for coreboot: DO NOT MERGE: Update esram_init.inc
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue May 17 18:33:38 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14875
-gerrit
commit 500ab7a370bcb83afe90303965f8e7718e84ddcd
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu May 12 07:19:45 2016 -0700
DO NOT MERGE: Update esram_init.inc
Update esram_init.c to match code in
QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat.S
Currently has GPIO test code in place, which needs to be removed:
* Sets stack
* Calls gpio_test
Change-Id: I76ce7730d0c385ea250885a34b7d7a171b541f62
---
src/soc/intel/quark/romstage/esram_init.inc | 189 +++++++++++++++++++---------
1 file changed, 127 insertions(+), 62 deletions(-)
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index b899741..dfa8217 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -52,6 +52,7 @@
/* RTC/CMOS definitions */
.equ RTC_INDEX, (0x70)
.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */
+.equ NMI_ENABLE, (0x00) /* Bit7=0 disables NMI */
.equ RTC_DATA, (0x71)
/* PCI Configuration definitions (Datasheet 5.5.1) */
@@ -75,16 +76,44 @@
/* Memory Arbiter Config Registers */
.equ AEC_CTRL_OFFSET, (0x00)
+/* Host Bridge PCI Config Registers */
+.equ MESSAGE_BUS_CONTROL_REG, (0xD0) /* Message Bus Control Register */
+.equ SB_OPCODE_FIELD, (0x18) /* Bit location of Opcode field */
+.equ OPCODE_SIDEBAND_REG_READ, (0x10) /* Read opcode */
+.equ OPCODE_SIDEBAND_REG_WRITE, (0x11) /* Write opcode */
+.equ OPCODE_SIDEBAND_ALT_REG_READ, (0x06) /* Alternate Read opcode */
+.equ OPCODE_SIDEBAND_ALT_REG_WRITE, (0x07) /* Alternate Write opcode */
+.equ OPCODE_WARM_RESET_REQUEST, (0xF4) /* Reset Warm */
+.equ OPCODE_COLD_RESET_REQUEST, (0xF5) /* Reset Cold */
+.equ SB_PORT_FIELD, (0x10) /* Bit location of Port ID field */
+.equ MEMORY_ARBITER_PORT_ID, (0x00)
+.equ HOST_BRIDGE_PORT_ID, (0x03)
+.equ RMU_PORT_ID, (0x04)
+.equ MEMORY_MANAGER_PORT_ID, (0x05)
+.equ SOC_UNIT_PORT_ID, (0x31)
+.equ SB_ADDR_FIELD, (0x08) /* Bit location of Register field */
+.equ SB_BE_FIELD, (0x04) /* Bit location of Byte Enables field */
+.equ ALL_BYTE_EN, (0x0F) /* All Byte Enables */
+.equ MESSAGE_DATA_REG, (0xD4) /* Message Data Register */
+
/* Host Bridge Config Registers */
+.equ HMISC2_OFFSET, (0x03) /* PCI configuration access mechanism */
+.equ OR_PM_FIELD, (0x10)
+
.equ HMBOUND_OFFSET, (0x08)
.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
+ QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
.equ HECREG_OFFSET, (0x09)
.equ EC_BASE, (0xE0000000)
.equ EC_ENABLE, (0x01)
+.equ HLEGACY_OFFSET, (0x0A)
+.equ NMI, (0x00004000)
+.equ SMI, (0x00001000)
+.equ INTR, (0x00000400)
/* Memory Manager Config Registers */
-.equ ESRAM_ADDRESS_2G, (0x10000080)
+.equ ESRAM_ADDRESS_2G, (0x80000000)
+.equ ESRAMPGCTRL_BLOCK_OFFSET, (0x82)
.equ BIMRVCTL_OFFSET, (0x19)
.equ ENABLE_IMR_INTERRUPT, (0x80000000)
@@ -127,16 +156,16 @@ setup_esram:
inb %dx, %al
/* Disable SMI (Disables SMI wire, not SMI messages) */
- movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx
leal L1, %esp
jmp stackless_SideBand_Read
L1:
andl $(~SMI_EN), %eax
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx
leal L2, %esp
jmp stackless_SideBand_Write
L2:
@@ -145,49 +174,49 @@ L2:
* Before we get going, check SOC Unit Registers to see if we are
* required to issue a warm/cold reset
*/
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) \
+ | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) \
+ | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx
leal L3, %esp
jmp stackless_SideBand_Read
L3:
andl $(FORCE_WARM_RESET), %eax
- jz TestForceColdReset /* No warm reset - branch */
+ jz TestForceColdReset /* No warm reset - branch */
jmp IssueWarmReset
TestForceColdReset:
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) \
+ | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) \
+ | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx
leal L4, %esp
jmp stackless_SideBand_Read
L4:
andl $(FORCE_COLD_RESET), %eax
- jz TestHmboundLock /* No cold reset - branch */
+ jz TestHmboundLock /* No cold reset - branch */
jmp IssueColdReset
/* Before setting HMBOUND, check it's not locked */
TestHmboundLock:
- movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx
leal L5, %esp
jmp stackless_SideBand_Read
L5:
andl $(HMBOUND_LOCK), %eax
- jz ConfigHmbound /* Good configuration - branch */
+ jz ConfigHmbound /* Good configuration - branch */
/* Failed to config - store sticky bit debug */
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) \
+ | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) \
+ | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
leal L6, %esp
jmp stackless_SideBand_Read
L6:
orl $(RESET_FOR_HMBOUND_LOCK), %eax
- movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) \
+ | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) \
+ | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
leal L7, %esp
jmp stackless_SideBand_Write
L7:
@@ -195,10 +224,10 @@ L7:
/* Set up the HMBOUND register */
ConfigHmbound:
- movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx
leal L8, %esp
jmp stackless_SideBand_Write
L8:
@@ -208,75 +237,101 @@ L8:
* violation occurs.
*/
movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) \
+ | (BIMRVCTL_OFFSET << SB_ADDR_FIELD)), %ecx
leal L9, %esp
jmp stackless_SideBand_Write
L9:
- /* Move eSRAM memory to 2GB */
+ /* Move eSRAM address */
movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
- << QNC_MCR_REG_OFFSET)), %ecx
+ shr $(0x18), %eax
+ addl $(BLOCK_ENABLE_PG), %eax
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) \
+ | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx
leal L10, %esp
jmp stackless_SideBand_Write
L10:
/* Check that we're not blocked from setting the config that we want. */
- movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
- << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) \
+ | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) \
+ | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx
leal L11, %esp
jmp stackless_SideBand_Read
L11:
andl $(BLOCK_ENABLE_PG), %eax
- jnz ConfigPci /* Good configuration - branch */
+ jnz ConfigPci /* Good configuration - branch */
/* Failed to config - store sticky bit debug */
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) \
+ | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) \
+ | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
leal L12, %esp
jmp stackless_SideBand_Read
L12:
orl $(RESET_FOR_ESRAM_LOCK), %eax
- movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) \
+ | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) \
+ | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx
leal L13, %esp
jmp stackless_SideBand_Write
L13:
- jmp IssueWarmReset
+ jmp IssueWarmReset
/* Enable PCIEXBAR */
ConfigPci:
movl $(EC_BASE + EC_ENABLE), %eax /* Data */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (MEMORY_ARBITER_PORT_ID << SB_PORT_FIELD) \
+ | (AEC_CTRL_OFFSET << SB_ADDR_FIELD)), %ecx
leal L14, %esp
jmp stackless_SideBand_Write
L14:
movl $(EC_BASE + EC_ENABLE), %eax /* Data */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HECREG_OFFSET << SB_ADDR_FIELD)), %ecx
leal L15, %esp
jmp stackless_SideBand_Write
L15:
/* Open up full 8MB SPI decode */
- movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */
+ movl $(PCI_CFG | (ILB_PFA << 8) | BDE), %ebx /* PCI Config address */
movl $(DECODE_ALL_REGIONS_ENABLE), %eax
leal L16, %esp
jmp stackless_PCIConfig_Write
L16:
+ /*
+ * Enable NMI operation
+ * Good convention suggests you should read back RTC data port after
+ * accessing the RTC index port.
+ */
+ movb $(NMI_ENABLE), %al
+ movw $(RTC_INDEX), %dx
+ outb %al, %dx
+ movw $(RTC_DATA), %dx
+ inb %dx, %al
+
+ /* Clear Host Bridge SMI, NMI, INTR fields */
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx
+ leal L21, %esp
+ jmp stackless_SideBand_Read
+L21:
+ andl $~(NMI + SMI + INTR), %eax /* Clear NMI, SMI, INTR fields */
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) \
+ | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) \
+ | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx
+ leal L22, %esp
+ jmp stackless_SideBand_Write
+L22:
+
jmp esram_init_done
IssueWarmReset:
@@ -320,8 +375,9 @@ stackless_SideBand_Read:
movl %esp, %esi /* Save the return address */
/* Load the SideBand Packet Register to generate the transaction */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
- movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) \
+ | (MESSAGE_BUS_CONTROL_REG)), %ebx
+ movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl /* Set all Byte Enables */
xchgl %ecx, %eax
leal L17, %esp
jmp stackless_PCIConfig_Write
@@ -329,7 +385,7 @@ L17:
xchgl %ecx, %eax
/* Read the SideBand Data Register */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx
leal L18, %esp
jmp stackless_PCIConfig_Read
L18:
@@ -365,14 +421,15 @@ stackless_SideBand_Write:
movl %esp, %esi /* Save the return address */
/* Load the SideBand Data Register with the data */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx
leal L19, %esp
jmp stackless_PCIConfig_Write
L19:
/* Load the SideBand Packet Register to generate the transaction */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
- movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) \
+ | (MESSAGE_BUS_CONTROL_REG)), %ebx
+ movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl /* Set all Byte Enables */
xchgl %ecx, %eax
leal L20, %esp
jmp stackless_PCIConfig_Write
@@ -452,6 +509,14 @@ stackless_PCIConfig_Read:
esram_init_done:
+ #
+ # Set up stack pointer
+ #
+ movl $CONFIG_FSP_ESRAM_LOC, %esp
+ movl $0x00040000, %esi
+ addl %esi, %esp # ESP = top of stack (stack grows downwards).
+ call gpio_test
+
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
/* Copy FSP image to eSRAM and call it. */
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