[coreboot-gerrit] New patch to review for coreboot: DO NOT MERGE: GPIO working
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue May 17 18:33:43 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14877
-gerrit
commit d2dffdcba42d10c58b6738c5141c6b3c2a7c9e4a
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun May 15 13:20:03 2016 -0700
DO NOT MERGE: GPIO working
Change-Id: I8f2a64307dc57188d1e7d91ba28c564655b5f116
---
src/soc/intel/quark/chip.c | 26 ++++++++++++++++++++++++++
src/soc/intel/quark/include/soc/reg_access.h | 3 +++
src/soc/intel/quark/reg_access.c | 1 +
src/soc/intel/quark/romstage/esram_init.inc | 10 +---------
src/soc/intel/quark/romstage/romstage.c | 26 --------------------------
5 files changed, 31 insertions(+), 35 deletions(-)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 21f09c9..4d5bafa 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -14,8 +14,13 @@
* GNU General Public License for more details.
*/
+//#define __SIMPLE_DEVICE__
+
#include <console/console.h>
#include <device/device.h>
+#include <device/pci_ids.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
@@ -100,6 +105,10 @@ static const struct reg_script thermal_init_script[] = {
static void chip_init(void *chip_info)
{
+ uint16_t command;
+ device_t dev;
+ uint32_t gpio_base_address;
+
/* Validate the temperature settings */
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
@@ -115,6 +124,23 @@ static void chip_init(void *chip_info)
== (TS_LOCK_THRM_CTRL_REGS_ENABLE
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
+ /* Configure the legacy GPIO controller */
+ dev = dev_find_slot(0, LPC_DEV_FUNC);
+ command = pci_read_config16(dev, PCI_COMMAND);
+printk(BIOS_ERR, "0x%08x --> 0x%04x\n", PCI_COMMAND, command);
+printk(BIOS_ERR, "0x%08x <-- 0x%04x\n", PCI_COMMAND, command | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_IO
+ | PCI_COMMAND_MASTER);
+
+ /* Set the GPIO controller base address if necessary */
+ gpio_base_address = pci_read_config32(dev, R_QNC_LPC_GBA_BASE);
+printk(BIOS_ERR, "0x%08x: gpio_base_address\n", gpio_base_address);
+ if (gpio_base_address == 0){
+ gpio_base_address = IO_ADDRESS_VALID | LEGACY_GPIO_BASE_ADDRESS;
+ pci_write_config32(dev, R_QNC_LPC_GBA_BASE, gpio_base_address);
+printk(BIOS_ERR, "0x%08x: gpio_base_address\n", gpio_base_address);
+ }
+
/* Initialize the PCIe bridges */
// reg_script_run(pcie_init_script);
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index 580400c..8491a2f 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -35,6 +35,8 @@ enum {
GPIO_REGS,
PCIE_AFE_REGS,
PCIE_RESET,
+ LEG_GPIO_REGS,
+ GPIO_REGS,
};
enum {
@@ -183,6 +185,7 @@ enum {
void *get_i2c_address(void);
void mainboard_gpio_init(void);
void mainboard_gpio_pcie_reset(uint32_t pin_value);
+void mainboard_gpio_init(void);
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index f7820e9..129eb49 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -198,6 +198,7 @@ static uint64_t reg_read(struct reg_script_context *ctx)
case LEG_GPIO_REGS:
ctx->display_prefix = "Legacy GPIO: ";
value = reg_legacy_gpio_read(step->reg);
+ break;
case PCIE_AFE_REGS:
ctx->display_prefix = "PCIe AFE: ";
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index dfa8217..82dca49 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -509,20 +509,12 @@ stackless_PCIConfig_Read:
esram_init_done:
- #
- # Set up stack pointer
- #
- movl $CONFIG_FSP_ESRAM_LOC, %esp
- movl $0x00040000, %esi
- addl %esi, %esp # ESP = top of stack (stack grows downwards).
- call gpio_test
-
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
/* Copy FSP image to eSRAM and call it. */
/* TODO: FSP location/size could be got in a routine. */
cld
- movl $(0x00040000), %ecx /* 256K DWORDs = 64K */
+ movl $(0x00050000), %ecx /* 320K DWORDs = 80K */
shrl $2, %ecx
movl $CONFIG_FSP_LOC, %esi /* The source address. */
movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index de1a767..31e492f 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -84,13 +84,6 @@ void car_soc_pre_console_init(void)
void car_soc_post_console_init(void)
{
-legacy_gpio_pin_value(0, 0);
-
- report_platform_info();
-
-/* Display the MTRRs */
-soc_display_mtrrs();
-
report_platform_info();
/* Initialize the controllers */
@@ -110,23 +103,6 @@ struct chipset_power_state *fill_power_state(void)
return ps;
}
-void gpio_test(void);
-#include <timestamp.h>
-
-void gpio_test(void)
-{
- /* Initialize timestamp book keeping only once. */
- timestamp_init(0);
-
- /* Call into pre-console init code then initialize console. */
- car_soc_pre_console_init();
- car_mainboard_pre_console_init();
- console_init();
-
- /* Test the GPIOs */
- legacy_gpio_pin_value(0, 0);
-}
-
/* Initialize the UPD parameters for MemoryInit */
void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd)
@@ -156,7 +132,6 @@ void soc_memory_init_params(struct romstage_params *params,
}
config = dev->chip_info;
-legacy_gpio_pin_value(0, 0);
/* Display the ROM shadow data */
hexdump((void *)0x000ffff0, 0x10);
}
@@ -180,7 +155,6 @@ void soc_after_ram_init(struct romstage_params *params)
/* Display the DRAM data */
hexdump((void *)0x000ffff0, 0x10);
-legacy_gpio_pin_value(0, 0);
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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