[coreboot-gerrit] New patch to review for coreboot: rockchip: rk3399: initialize display for eDP
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Mon May 16 23:09:23 CEST 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14857
-gerrit
commit c71cbc61e3d070055943d14ec9d90be487289348
Author: Shunqian Zheng <zhengsq at rock-chips.com>
Date: Wed May 4 16:21:36 2016 +0800
rockchip: rk3399: initialize display for eDP
This patch add functions to init display. To setup display,
initialize the eDP and read EDID, basing on which we then
set the clock for VOP, and finally enable VOP and backlight.
For a mainboard, it should set the vop_id, vop_mode and
framebuffer_bits_per_pixel in devicetree.cb.
For VOP_MODE_AUTO_DETECT, it will try eDP first and then
HDMI(which is not supported yet).
BRANCH=none
BUG=chrome-os-partner:51537
TEST=test with the other patch
Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a
Signed-off-by: Martin Roth <martinroth at google.com>
Original-Commit-Id:
Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761
Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342336
Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Reviewed-by: Shunqian Zheng <zhengsq at rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
---
src/soc/rockchip/rk3399/Makefile.inc | 3 +
src/soc/rockchip/rk3399/chip.h | 32 ++++++
src/soc/rockchip/rk3399/display.c | 122 +++++++++++++++++++++++
src/soc/rockchip/rk3399/include/soc/addressmap.h | 5 +
src/soc/rockchip/rk3399/include/soc/display.h | 25 +++++
src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 +
src/soc/rockchip/rk3399/soc.c | 8 ++
7 files changed, 196 insertions(+)
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 68f346c..edee10f 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -55,6 +55,8 @@ ramstage-y += sdram.c
ramstage-y += ../common/spi.c
ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
ramstage-y += clock.c
+ramstage-y += display.c
+ramstage-y += ../common/edp.c
ramstage-y += emmc.c
ramstage-y += ../common/gpio.c
ramstage-y += gpio.c
@@ -62,6 +64,7 @@ ramstage-y += ../common/i2c.c
ramstage-y += saradc.c
ramstage-y += soc.c
ramstage-y += timer.c
+ramstage-y += ../common/vop.c
BL31_MAKEARGS += PLAT=rk3399
################################################################################
diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h
new file mode 100644
index 0000000..46baa8c
--- /dev/null
+++ b/src/soc/rockchip/rk3399/chip.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_CHIP_H__
+#define __SOC_ROCKCHIP_RK3399_CHIP_H__
+
+#include <soc/gpio.h>
+#include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */
+
+struct soc_rockchip_rk3399_config {
+ u32 vop_id;
+ gpio_t lcd_bl_pwm_gpio;
+ gpio_t lcd_bl_en_gpio;
+ u32 bl_power_on_udelay;
+ u32 bl_pwm_to_enable_udelay;
+ u32 framebuffer_bits_per_pixel;
+ u32 vop_mode;
+};
+
+#endif /* __SOC_ROCKCHIP_RK3399_CHIP_H__ */
diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c
new file mode 100644
index 0000000..25389b0
--- /dev/null
+++ b/src/soc/rockchip/rk3399/display.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cache.h>
+#include <arch/mmu.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <edid.h>
+#include <gpio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <string.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/display.h>
+#include <soc/edp.h>
+#include <soc/gpio.h>
+#include <soc/grf.h>
+#include <soc/mmu_operations.h>
+#include <soc/soc.h>
+#include <soc/vop.h>
+
+#include "chip.h"
+
+void rk_display_init(device_t dev, uintptr_t lcdbase,
+ unsigned long fb_size)
+{
+ struct edid edid;
+ uint32_t val;
+ struct soc_rockchip_rk3399_config *conf = dev->chip_info;
+ uintptr_t lower = ALIGN_DOWN(lcdbase, MiB);
+ uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
+ enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
+
+ printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase));
+ memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
+ dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
+ mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM);
+
+ switch (conf->vop_mode) {
+ case VOP_MODE_NONE:
+ return;
+ case VOP_MODE_AUTO_DETECT:
+ /* try EDP first, then HDMI */
+ case VOP_MODE_EDP:
+ printk(BIOS_DEBUG, "Attempting to setup EDP display.\n");
+ rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
+
+ /* select edp signal from vop0(big) or vop1(little) */
+ val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) :
+ RK_CLRBITS(1 << 5);
+ write32(&rk3399_grf->soc_con20, val);
+
+ /* select edp clk from SoC interal 24M crystal, otherwise,
+ * it will source from edp's 24M clock(that depends on
+ * edp vendor, could be unstable)
+ */
+ write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
+
+ rk_edp_init();
+
+ if (rk_edp_get_edid(&edid) == 0) {
+ detected_mode = VOP_MODE_EDP;
+ break;
+ }
+ printk(BIOS_WARNING, "Cannot get EDID from EDP.\n");
+ if (conf->vop_mode == VOP_MODE_EDP)
+ return;
+ /* fall thru */
+ case VOP_MODE_HDMI:
+ printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n");
+ return;
+ default:
+ printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n");
+ return;
+ }
+
+ if (rkclk_configure_vop_dclk(conf->vop_id,
+ edid.mode.pixel_clock * KHz)) {
+ printk(BIOS_WARNING, "config vop err\n");
+ return;
+ }
+
+ edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel;
+ edid.bytes_per_line =
+ edid.mode.ha * conf->framebuffer_bits_per_pixel / 8;
+ edid.x_resolution = edid.mode.ha;
+ edid.y_resolution = edid.mode.va;
+ rkvop_mode_set(conf->vop_id, &edid, detected_mode);
+
+ rkvop_enable(conf->vop_id, lcdbase, &edid);
+
+ switch (detected_mode) {
+ case VOP_MODE_HDMI:
+ /* should not be here before HDMI supported */
+ return;
+ case VOP_MODE_EDP:
+ default:
+ if (rk_edp_enable()) {
+ printk(BIOS_WARNING, "edp enable err\n");
+ return;
+ }
+ mainboard_power_on_backlight();
+ break;
+ }
+
+ set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase);
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index 28cbd7a..6d494fd 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -59,6 +59,11 @@
#define TSADC_BASE 0xff260000
#define SARADC_BASE 0xff100000
#define RK_PWM_BASE 0xff420000
+#define EDP_BASE 0xff970000
+
+#define VOP_BIG_BASE 0xff900000 /* corresponsed to vop_id 0 */
+#define VOP_LIT_BASE 0xff8f0000 /* corresponsed to vop_id 1 */
+
#define DDRC0_BASE_ADDR 0xffa80000
#define SERVER_MSCH0_BASE_ADDR 0xffa84000
diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h
new file mode 100644
index 0000000..7ccde56
--- /dev/null
+++ b/src/soc/rockchip/rk3399/include/soc/display.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_DISPLAY_H__
+#define __SOC_ROCKCHIP_RK3399_DISPLAY_H__
+
+#define REF_CLK_24M (0x1 << 0)
+
+void rk_display_init(device_t dev, uintptr_t lcdbase,
+ unsigned long fb_size);
+void mainboard_power_on_backlight(void);
+
+#endif
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index edb246d..ac16394 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -22,6 +22,7 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x00100000, 1M)
RAMSTAGE(0x00300000, 256K)
DMA_COHERENT(0x10000000, 2M)
+ FRAMEBUFFER(0x10200000, 8M)
SRAM_START(0xFF8C0000)
BOOTBLOCK(0xFF8C2004, 32K - 4)
diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index 5b6ddb2..733c7d8 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -13,10 +13,12 @@
* GNU General Public License for more details.
*/
+#include <bootmode.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <device/device.h>
#include <soc/addressmap.h>
+#include <soc/display.h>
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
@@ -34,6 +36,12 @@ static void soc_init(device_t dev)
* arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h
*/
mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB));
+
+ if (display_init_required())
+ rk_display_init(dev, (uintptr_t)_framebuffer,
+ _framebuffer_size);
+ else
+ printk(BIOS_INFO, "Skipping display init.\n");
}
static struct device_operations soc_ops = {
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