[coreboot-gerrit] New patch to review for coreboot: rockchip: rk3399: enable sdhci clk for emmc

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14856

-gerrit

commit bbccb35b1902fbebbbc9182905ade300084e1fa6
Author: Shunqian Zheng <zhengsq at rock-chips.com>
Date:   Mon May 2 10:27:30 2016 +0800

    rockchip: rk3399: enable sdhci clk for emmc
    
    If booting from sdcard/usb, kernel can't recognize the
    /dev/mmcblk0.
    Before kernel find it's root cause, we add this workaround
    patch to enable clk for emmc.
    
    BRANCH=none
    BUG=chrome-os-partner:52873
    TEST=boot from sdcard and check the /dev/mmcblk0 exists
    
    Change-Id: Ie36cc6fdbc24db8c30984c02ccfe2f8aaaf30cd2
    Signed-off-by: Martin Roth <martinroth at google.com>
    Original-Commit-Id:
    Original-Change-Id: I88a9cc2e3ea5a56aadfdbd94ef910daaf92a7eb7
    Original-Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/341632
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/mainboard/google/gru/mainboard.c       |  3 ++
 src/soc/rockchip/rk3399/Makefile.inc       |  1 +
 src/soc/rockchip/rk3399/emmc.c             | 50 ++++++++++++++++++++++++++++++
 src/soc/rockchip/rk3399/include/soc/emmc.h | 16 ++++++++++
 4 files changed, 70 insertions(+)

diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 6d2b4f4..6824cbf 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -18,6 +18,7 @@
 #include <device/device.h>
 #include <gpio.h>
 #include <soc/clock.h>
+#include <soc/emmc.h>
 #include <soc/grf.h>
 
 static void configure_emmc(void)
@@ -32,6 +33,8 @@ static void configure_emmc(void)
 	write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
 
 	rkclk_configure_emmc();
+
+	enable_emmc_clk();
 }
 
 static void configure_sdmmc(void)
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 9af451c..68f346c 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -55,6 +55,7 @@ ramstage-y += sdram.c
 ramstage-y += ../common/spi.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 ramstage-y += clock.c
+ramstage-y += emmc.c
 ramstage-y += ../common/gpio.c
 ramstage-y += gpio.c
 ramstage-y += ../common/i2c.c
diff --git a/src/soc/rockchip/rk3399/emmc.c b/src/soc/rockchip/rk3399/emmc.c
new file mode 100644
index 0000000..b8519f7
--- /dev/null
+++ b/src/soc/rockchip/rk3399/emmc.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/emmc.h>
+
+#define SDHCI_CLOCK_CONTROL	0x2c
+#define SDHCI_CLOCK_CARD_EN	0x0004
+#define SDHCI_CLOCK_INT_STABLE	0x0002
+#define SDHCI_CLOCK_INT_EN	0x0001
+
+/* TODO(crosbug.com/p/52873): We actually don't need to set clk for
+ * emmc once kernel fix it's bug.
+ */
+void enable_emmc_clk(void)
+{
+	int timeout, clk;
+
+	write32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL), SDHCI_CLOCK_INT_EN);
+
+	/* Wait max 20 ms */
+	timeout = 20;
+	while (!((clk = read32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL)))
+		& SDHCI_CLOCK_INT_STABLE)) {
+		if (timeout == 0) {
+			printk(BIOS_ERR, "Internal clock never stabilised.\n");
+			return;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	clk |= SDHCI_CLOCK_CARD_EN;
+	write32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL), clk);
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/emmc.h b/src/soc/rockchip/rk3399/include/soc/emmc.h
new file mode 100644
index 0000000..0d29d9e
--- /dev/null
+++ b/src/soc/rockchip/rk3399/include/soc/emmc.h
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+void enable_emmc_clk(void);