[coreboot-gerrit] New patch to review for coreboot: intel/fsp1_1: Adding C entry support to locate FSP Temp RAM Init
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Fri Jul 22 15:26:07 CEST 2016
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15787
-gerrit
commit c97db78dd6a79c943772e3d54cfdbb686f9e42f0
Author: Subrata Banik <subrata.banik at intel.com>
Date: Fri Jul 22 00:10:53 2016 +0530
intel/fsp1_1: Adding C entry support to locate FSP Temp RAM Init
FSP temp ram init was getting called earlier from ROMCC bootblock.
Now with C entry boot block, need to locate FSP header to call FSP
Temp Init.
Hence adding fsp 1_1 driver code to locate FSP Temp ram and execute.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Build and ensure FSP Temp Ram Init return success
Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/console/Makefile.inc | 1 +
src/drivers/intel/fsp1_1/Makefile.inc | 3 ++
src/drivers/intel/fsp1_1/bootblock.c | 49 ++++++++++++++++++++++++
src/drivers/intel/fsp1_1/include/fsp/bootblock.h | 24 ++++++++++++
src/soc/intel/skylake/bootblock/bootblock.c | 2 +
5 files changed, 79 insertions(+)
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 0fee12a..68afb8a 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -25,4 +25,5 @@ postcar-y += die.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c
+bootblock-y += post.c
bootblock-y += die.c
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 011df67..397bad8 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -20,6 +20,9 @@ verstage-y += car.c
verstage-y += fsp_util.c
verstage-y += verstage.c
+bootblock-y += bootblock.c
+bootblock-y += fsp_util.c
+
romstage-y += car.c
romstage-y += fsp_util.c
romstage-y += hob.c
diff --git a/src/drivers/intel/fsp1_1/bootblock.c b/src/drivers/intel/fsp1_1/bootblock.c
new file mode 100644
index 0000000..1af907c
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/bootblock.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/bootblock.h>
+
+static void soc_temp_ram_init_params(FSP_TEMP_RAM_INIT_PARAMS *params)
+{
+ params->MicrocodeRegionBase = CONFIG_CPU_MICROCODE_CBFS_LOC;
+ params->MicrocodeRegionLength = CONFIG_CPU_MICROCODE_CBFS_LEN;
+ params->CodeRegionBase = 0xFFFFFFFF - CONFIG_ROM_SIZE + 1;
+ params->CodeRegionLength = CONFIG_ROM_SIZE;
+}
+
+void bootblock_fsp_temp_ram_init(void)
+{
+ FSP_TEMP_RAM_INIT fsp_temp_ram_init;
+ FSP_TEMP_RAM_INIT_PARAMS temp_ram_init_params;
+ FSP_INFO_HEADER *fih;
+ EFI_STATUS status;
+
+ /* Locate the FSP header */
+ fih = find_fsp(CONFIG_FSP_LOC);
+ /* Check the FSP header */
+ if (fih == NULL) {
+ printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
+ return;
+ }
+ soc_temp_ram_init_params(&temp_ram_init_params);
+ /* Perform Temp RAM Init */
+ printk(BIOS_DEBUG, "Calling FspTempRamInit\n");
+ post_code(POST_FSP_TEMP_RAM_INIT);
+ fsp_temp_ram_init = (FSP_TEMP_RAM_INIT)(fih->ImageBase
+ + fih->TempRamInitEntryOffset);
+ status = fsp_temp_ram_init(&temp_ram_init_params);
+ printk(BIOS_DEBUG, "FspTempRamInit returned 0x%08x\n", status);
+}
\ No newline at end of file
diff --git a/src/drivers/intel/fsp1_1/include/fsp/bootblock.h b/src/drivers/intel/fsp1_1/include/fsp/bootblock.h
new file mode 100644
index 0000000..08a1179
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/bootblock.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef FSP1_1_BOOTBLOCK_H
+#define FSP1_1_BOOTBLOCK_H
+
+#include <fsp/util.h>
+#include <stdint.h>
+
+void bootblock_fsp_temp_ram_init(void);
+
+#endif
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 533728e..8415b17 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -10,6 +10,7 @@
*/
#include <bootblock_common.h>
#include <soc/bootblock.h>
+#include <fsp/bootblock.h>
void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
{
@@ -29,5 +30,6 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
+ bootblock_fsp_temp_ram_init();
pch_enable_lpc();
}
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