[coreboot-gerrit] New patch to review for coreboot: BCRD2: Enable PMIC SVID config

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11060

-gerrit

commit 50178a69b7a7816af0af41a6e6bf2cf1158ff915
Author: Jenny TC <jenny.tc at intel.com>
Date:   Thu Jun 18 14:55:10 2015 +0530

    BCRD2: Enable PMIC SVID config
    
    Enable PMIC SVID config for BCRD2 based
    on board id. UPD parameter is used to
    select the SVID config and PMIC I2C bus
    number
    
    BRANCH=None
    BUG=None
    TEST=Build and boot the system
    
    Change-Id: I3c4c06bd25c241abdf46aa14af74eecf77cf77a6
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
    Original-Commit-Id: 10bb8d4ad96d1187f6e135ca1535d70ae45ee887
    Original-Change-Id: I9191db7bace4f4840e3c32381093c6c0806f7c32
    Original-Signed-off-by: Jenny TC <jenny.tc at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/282156
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/braswell/chip.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index d70aa9b..7422bc4 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -30,8 +30,9 @@
 #include <fsp_util.h>
 #include <soc/pci_devs.h>
 
-#define SVID_CONFIG1	1
-#define SVID_CONFIG3	3
+#define SVID_CONFIG1		1
+#define SVID_CONFIG3		3
+#define SVID_PMIC_CONFIG	8
 
 struct soc_intel_braswell_config {
 	uint8_t enable_xdp_tap;