[coreboot-gerrit] New patch to review for coreboot: 6f055b5 pistachio: increase size of bootblock to 18 KB

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9665

-gerrit

commit 6f055b5a2c894e1fe512b6cd13bcefe5e4d347ce
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Mon Jan 26 13:29:34 2015 +0000

    pistachio: increase size of bootblock to 18 KB
    
    With the added code for clock and MFIOs setup, bootblock
    now exceeds 16KB. This patch increases the allowed limit
    to 18KB.
    
    BUG=chrome-os-partner:31438
    TEST=tested on Pistachio bring up board; works as expected
    BRANCH=none
    
    Change-Id: I166f882bd3db446bcd6f9e1f828cab22266c6ac7
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: da95db5ed348419b7905dc1ab68fd64d7b2eb5e0
    Original-Change-Id: I0cacc6163f21ae3673c2716b12dde66bd48290f9
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/243213
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 7538762..5b50a0a 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -28,9 +28,9 @@ SECTIONS
 
 	/* GRAM becomes the SRAM. */
 	SRAM_START(0x9a000000)
-	BOOTBLOCK(0x9a000000, 16K)
-	ROMSTAGE(0x9a004000, 36K)
-	CBFS_CACHE(0x9a00d000, 76K)
+	BOOTBLOCK(0x9a000000, 18K)
+	ROMSTAGE(0x9a004800, 36K)
+	CBFS_CACHE(0x9a00d800, 74K)
 	SRAM_END(0x9a020000)
 
 	/* Let's use SRAM for stack and CBMEM console. */