[coreboot-gerrit] New patch to review for coreboot: 2a3461d pistachio: Use 1.8433179 MHz for UART refclk

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9666

-gerrit

commit 2a3461d7dafd1c9dba468b92bf063f5c68d16d37
Author: David Hendricks <dhendrix at chromium.org>
Date:   Mon Jan 26 07:19:49 2015 -0800

    pistachio: Use 1.8433179 MHz for UART refclk
    
    BUG=chrome-os-partner:31438
    BRANCH=none
    TEST=built and booted on urara w/ follow-up patches
    
    Change-Id: I3b03ce937e68539343e58b01e3bb714dd1f8c2dd
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 9493c57a14c8ab074baac1c065c6f39050dd9b2f
    Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Original-Change-Id: I8e50c99913ea155ba0d5699f4789c1fe38b46808
    Original-Reviewed-on: https://chromium-review.googlesource.com/243210
    Original-Reviewed-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
 src/soc/imgtec/pistachio/uart.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
index 9c96b89..b589289 100644
--- a/src/soc/imgtec/pistachio/uart.c
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -118,8 +118,8 @@ static void uart8250_mem_init(unsigned base_port, unsigned divisor)
 
 unsigned int uart_platform_refclk(void)
 {
-	/* TODO: this is entirely arbitrary */
-	return 1000000;
+	/* 1.8433179 MHz */
+	return 1843318;
 }
 
 uintptr_t uart_platform_base(int idx)