[coreboot-gerrit] New patch to review for coreboot: 22714ed pistachio: change memory layout as to allow bigger CBFS cache

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9664

-gerrit

commit 22714ed6eee7f65d2bc17088ebe1866f831f9a17
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Thu Dec 18 13:58:21 2014 +0000

    pistachio: change memory layout as to allow bigger CBFS cache
    
    As the payload increases in size, a bigger CBFS cache is required.
    Therfore, bootblock, romstage and the cbfs cache were placed in
    GRAM (128 K) and the stack and cbmem console were moved to
    SRAM (64 K). With the exception of CBFS cache, the sizes of all
    the other regions remains the same.
    
    BUG=chrome-os-partner:31438
    TEST=tested on Pistachio FPGA and bring up board;
         behavior was as expected.
    BRANCH=none
    
    Change-Id: I19857f785ca1514f7483d582c7ad6ee470a8fefc
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: c895660dbdcd113bdc9d832beab30886313c28d6
    Original-Change-Id: I004f8f081d04f83e3f5cee969e50803685cfdf67
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/236551
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index c3c6c07..7538762 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -30,12 +30,13 @@ SECTIONS
 	SRAM_START(0x9a000000)
 	BOOTBLOCK(0x9a000000, 16K)
 	ROMSTAGE(0x9a004000, 36K)
-	STACK(0x9a01c000, 8K)
-	PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
+	CBFS_CACHE(0x9a00d000, 76K)
 	SRAM_END(0x9a020000)
 
-	/* Let's use SRAM for CBFS cache. */
-	CBFS_CACHE(0x9b000000, 64K)
+	/* Let's use SRAM for stack and CBMEM console. */
+	STACK(0x9b000000, 8K)
+	PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
+
 	/* DMA coherent area: end of available DRAM, uncached */
 	DMA_COHERENT(0xAFF00000, 1M)
 }