[SeaBIOS] [PATCH v2] Make pci memory window configurable.
kevin at koconnor.net
Wed May 4 02:47:04 CEST 2011
On Tue, May 03, 2011 at 12:34:42PM +0200, Gerd Hoffmann wrote:
> >>Is there any reason why there is a fixed split, other than making
> >>the code simpler (i.e. need only one instead of two passes over all
> >>pci devices)?
> >I think the only reason is that a two pass PCI scan is more work than
> >anyone wanted to do.
> Are there any alignment requirements for the two pci memory windows,
> other than the ones dictated by pci bars in there? To create mtrr
> entries for the prefetchable memory maybe?
I don't know of any alignment restrictions other than that specified
in the BAR. SeaBIOS doesn't setup MTRRs right now for pref mem.
Looks like each bus uses 1meg alignment for all devices on that bus.
> Is there a way to figure the usable address space at runtime instead
> of depending on BUILD_PCIMEM_START? Can I just check RamSize?
As far as I'm aware, it would be possible to use RamSize (or better
yet, the e820 map).
I'm not really an expert here though - Isaku may know more.
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