[OpenBIOS] More work on Solaris 8 SPARC32 crash

Blue Swirl blauwirbel at gmail.com
Sun Feb 13 22:57:15 CET 2011

On Sun, Feb 13, 2011 at 11:23 PM, Mark Cave-Ayland
<mark.cave-ayland at siriusit.co.uk> wrote:
> On 13/02/11 20:50, Blue Swirl wrote:
>>> So my next question is that if OpenBIOS is supposed to handle the level
>>> 14
>>> timer, what should it doing with it? And is there a relationship between
>>> the
>>> level 14 timer and level 10 timer which causes one to trigger the other?
>> Nice work! Maybe OBP uses it to blink the cursor or poll some devices.
>> If we don't use the level 14 interrupt, it should be handled but
>> ignored. About level 10 timer, maybe OpenBIOS should program it
>> initially so that it won't cause interrupts.
> I did find something that may be useful here:
> http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
> <quote>
> The interrupt is cleared and the limit bits reset by reading
> the appropriate limit register.  Reading the counter register does not
> change the state of the limit bit.  Writing the limit register resets
> the corresponding counter to 500nS (0x200).
> </quote>
> So does that mean that the OpenBIOS timer handlers need to read the limit
> register in order to reset the interrupt status? Then again, I'm not
> convinced by this is the total solution since if I add breakpoints on
> irq_entry10 and irq_entry14 then they never seem to hit in gdb anyhow.

Right. Then I'd try to program the timer and also interrupt
controller. In theory also PIL level could matter if the OS preserved
the value which was used when it took charge, but I doubt this.

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