[OpenBIOS] More work on Solaris 8 SPARC32 crash

Mark Cave-Ayland mark.cave-ayland at siriusit.co.uk
Mon Feb 14 11:19:10 CET 2011

On 13/02/11 21:57, Blue Swirl wrote:

>> So does that mean that the OpenBIOS timer handlers need to read the limit
>> register in order to reset the interrupt status? Then again, I'm not
>> convinced by this is the total solution since if I add breakpoints on
>> irq_entry10 and irq_entry14 then they never seem to hit in gdb anyhow.
> Right. Then I'd try to program the timer and also interrupt
> controller. In theory also PIL level could matter if the OS preserved
> the value which was used when it took charge, but I doubt this.

I'm wondering if there is actually a qemu bug here too, since the 
documentation also mentions the following:

"When a counter reached the value in its corresponding
limit register, it is reset to 500ns (i.e. 0x00000200)"

and also:

"Writing the limit register resets the corresponding counter to 500nS 

AFAICT looking at slavio_timer.c I can't see a 0x200 initial base when 
the timer is reset - Blue, what do you think? I'm trying to figure out 
why writing a non-zero value to the limit register seems to get the L14 
timer to return something non-zero, whereas in theory with a limit set 
to 0 it should be free-running and with a base limit of 0x200 set, never 
return a zero value.



Mark Cave-Ayland - Senior Technical Architect
PostgreSQL - PostGIS
Sirius Corporation plc - control through freedom
t: +44 870 608 0063

Sirius Labs: http://www.siriusit.co.uk/labs

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