[OpenBIOS] ppc64 MMU issues

Andreas Färber andreas.faerber at web.de
Mon Nov 8 20:01:02 CET 2010

Am 08.11.2010 um 10:34 schrieb Mark Cave-Ayland:

> Andreas Färber wrote:
>> Directly after we set the MSR_IR|MSR_DR bits in the MSR (arch/ppc/ 
>> qemu/ofmem.c:setup_mmu), we get an ISI exception and end up in arch/ 
>> ppc/qemu/start.S:vector__0x400 (the 0xfffxxxxx one). We proceed up  
>> to the bctrl which should take us to arch/ppc/qemu/ 
>> ofmem.c:isi_exception, but then get a 0x700 program exception. The  
>> value in ctr looks sensible, it's some 0xfffxxxxx address.
> Hmmm this sounds similar to a SPARC32 issue I was finding over the  
> weekend whereby everything died after the MMU was enabled because  
> the context table wasn't correctly aligned. Could it be possible  
> that the MMU hash tables aren't aligned correctly in memory?

Recently I fixed some memory layout calculations and we decided to use  
the ppc64 alignment even on ppc, so we should be okay.
32-bit ppc code disables the 64-bit mode right away and in every  
interrupt handler; disabling it in the 64-bit ppc64 interrupt handler  
gave no improvement though.

I had tried packing the structs used for the page table, without  
noticable effect:


Not sure if that is necessary? It would same safer to me.


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