[OpenBIOS] L2 cache
dave at denial.force9.co.uk
Tue Aug 26 17:19:50 CEST 2003
Ronald G Minnich <rminnich at lanl.gov> wrote:
> > Other systems (Celeron, P2/P3[xeon]/p4?, K6-2/3, Athlon] have
> > their caches onboard and require MSR poking. This should be in
> > the BIOS writers guides for the respective CPUs.
> we're just trying to find that darn bit. Any hints :-)
It's not just a case of setting one bit. You have to set up a whole
bunch of other stuff, latencies, ranges, frequencies etc.
I'll dig some more, I've got example code somewhere.
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