[flashrom] [PATCH] Add board enable for Asus DSAN-DX.

[Stefan Tauner]

IDs are from the host bridge and LPC controller. The enable function
was reverse engineered by roxfan, thanks!

Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
---

Hello mezzo,

we have hopefully figured out how the write protection can be disabled.
you need to apply the following patch to the source code of flashrom and
recompile it.
see http://flashrom.org/Download#Installation_from_source for details...

when you have recompiled it successfully, please send us the output of
flashrom -p internal -V and retry writing, thanks.

diff --git a/board_enable.c b/board_enable.c
index 8f0219e..cfba5b9 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1823,6 +1823,7 @@ static int intel_ich_gpio26_raise(void)
 
 /*
  * Suited for:
+ *  - ASUS DSAN-DX
  *  - P4SD-LA (HP OEM): i865 + ICH5
  *  - GIGABYTE GA-8IP775: 865P + ICH5
  *  - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
@@ -2335,6 +2336,7 @@ const struct board_match board_matches[] = {
 	{0x10DE, 0x0260, 0x103C, 0x2A34,  0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3",    NULL, NULL,           P3, "ASUS",        "A8M2N-LA (NodusM3-GL8E)",  0,   OK, nvidia_mcp_gpio0_raise},
 	{0x10DE, 0x0260, 0x103c, 0x2a3e,  0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L",   NULL, NULL,           P3, "ASUS",        "A8N-LA (Nagami-GL8E)",  0,   OK, nvidia_mcp_gpio0_raise},
 	{0x10de, 0x0264, 0x1043, 0x81bc,  0x10de, 0x02f0, 0x1043, 0x81cd, NULL,         NULL, NULL,           P3, "ASUS",        "A8N-VM CSM",            0,   OK, w83627ehf_gpio22_raise_2e},
+	{0x8086, 0x65c0, 0x1043, 0x8301,  0x8086, 0x2916, 0x1043, 0x82a6, "^DSAN-DX$",  NULL, NULL,           P3, "ASUS",        "DSAN-DX",               0,   OK, intel_ich_gpio32_raise},
 	{0x10DE, 0x0264, 0x1043, 0x81C0,  0x10DE, 0x0260, 0x1043, 0x81C0, NULL,         NULL, NULL,           P3, "ASUS",        "M2NBP-VM CSM",          0,   OK, nvidia_mcp_gpio0_raise},
 	{0x1106, 0x1336, 0x1043, 0x80ed,  0x1106, 0x3288, 0x1043, 0x8249, NULL,         NULL, NULL,           P3, "ASUS",        "M2V-MX",                0,   OK, via_vt823x_gpio5_raise},
 	{0x8086, 0x24cc,      0,      0,  0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$",     NULL, NULL,           P3, "ASUS",        "M6Ne",                  0,   NT, intel_ich_gpio43_raise},
diff --git a/print.c b/print.c
index 5a27320..2092b5a 100644
--- a/print.c
+++ b/print.c
@@ -634,6 +634,7 @@ const struct board_info boards_known[] = {
 	B("ASUS",	"A8V-E SE",		OK, "http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html"),
 	B("ASUS",	"Crosshair II Formula",	OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/Crosshair_II_Formula/", NULL),
 	B("ASUS",	"Crosshair IV Extreme",	OK, "http://www.asus.com/Motherboards/AMD_AM3/Crosshair_IV_Extreme/", NULL),
+	B("ASUS",	"DSAN-DX",		OK, "http://www.asus.com/Server_Workstation/Server_Motherboards/DSANDX/", NULL),
 	B("ASUS",	"E35M1-I DELUXE",	OK, "http://www.asus.com/Motherboards/AMD_CPU_on_Board/E35M1I_DELUXE/", NULL),
 	B("ASUS",	"K8N",			OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8N/", NULL),
 	B("ASUS",	"K8V",			OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V/", NULL),
-- 
Kind regards, Stefan Tauner