[flashrom] RFC: conditionalize delays in JEDEC erase instructions

[Carl-Daniel Hailfinger]

Auf 05.03.2011 23:57, Michael Karcher schrieb:
> Hello Carl-Daniel,
>
> Am Samstag, den 05.03.2011, 22:30 +0100 schrieb Carl-Daniel Hailfinger:
>   
>>> If I understand it correctly, the delays in erase_sector_jedec_common
>>> are mostly for chips that need commands to be written so slowly - these
>>> chips should require a probe delay, too. So would there be a problem to
>>> put these delays into a "probe timing not zero" test?
>>>   
>>>       
>> AFAIK the erase delay is used on chips which need the probe delay
>> anyway, so your test would indeed cover those problems. However, there
>> is one exception: Winbond W39V040C. See the mail at
>> http://www.flashrom.org/pipermail/flashrom/2009-December/001330.html We
>> could add a new feature bit for this...
>>     
> I don't see how that is related, except for also covering some erase
> problems. My idea was about removing the delays between the command
> bytes, while that patch slows down the toggle bit detection. I did not
> intent to change the toggle bit stuff or use the non-slow call. Do I
> miss something?
>   

Ah OK, misunderstanding on my side. Please go ahead.

Regards,
Carl-Daniel

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