[coreboot] How to get correct memory params for FSP

Alex Feinman alexfeinman at hotmail.com
Tue Nov 6 18:45:39 CET 2018

Guilty as charged :)

From: R S <rene.shuster at bcsemail.org>
Sent: Tuesday, November 6, 2018 9:30 AM
To: alexfeinman at hotmail.com
Cc: coreboot at coreboot.org; alexey_bau at mail.ru
Subject: Re: [coreboot] How to get correct memory params for FSP

Faint memories... are you the ISO recorder author from 15 years ago?

On Tue, Nov 6, 2018 at 12:23 PM Alex Feinman <alexfeinman at hotmail.com<mailto:alexfeinman at hotmail.com>> wrote:
The two major issues with bringing up the memory subsystem on a new board are SPD parameters and DQ/DQS layout
Specifically, if you look at the apollolake rvp subtree, you can see a whole bunch of parameters being set in romstage.c. Some of it is fairly straightforward. Swizzling tables are not and require you to be able to read schematic (and have access to it in the first place)
Obviously, the problem could be elsewhere. I would start with enabling MRC debug and perhaps posting the MRC output

From: coreboot <coreboot-bounces at coreboot.org<mailto:coreboot-bounces at coreboot.org>> on behalf of Alexey Borovikov via coreboot <coreboot at coreboot.org<mailto:coreboot at coreboot.org>>
Sent: Saturday, November 3, 2018 5:38 AM
To: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
Subject: [coreboot] How to get correct memory params for FSP

I port the Coreboot to a board with an SOC Intel Atom E3845 and use FSP for the Baytrail family. The result - postcode is 0x2A. From the descriptions on the Internet, I understand that the problem is in the incorrect memory parameters.
Question: are there any utilities or methods that will help to get the correct memory parameters when working a regular BIOS from Linux or Windows systems?
Many thanks!
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