[coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Timothy Pearson tpearson at raptorengineering.com
Mon Jun 25 17:55:22 CEST 2018

On 06/25/2018 10:45 AM, Peter Stuge wrote:
> ron minnich wrote:
>> I realize there was a lot of hope in the early days that RISC-V
>> implied "openness" but as we can see that is not so.
> I hope that noone had that impression.
> The key point (which I have to repeat every now and then) is that
> RISC-V *supports* openness, in ways not possible with x86, ARM or
> -yes- even POWER, at least at the moment.
>> An open implementation of RISC-V will require a commitment on the
>> part of a company to opening it up at all levels, not just the
>> instruction set.
> ron minnich wrote:
>> I'm still interested in risc-v, just not hifive.
> Right - I think it's important not to judge an open architecture by
> any one implementation, but to remember (as you point out) the
> difference between architecture and implementation.
> //Peter

The problem as I see it is that the two are inextricably tied.  You can
have a completely open architecture and no open implementations -- in
fact, this is the case right now with the Sparc T2.  I can run the HDL
on an FPGA or even fab a chip with the right resources, but there is no
reason to actually fab a chip, nor do I personally have the resources to
do so.

In practice, publicly available implementations are what determine the
actual openness of an architecture.  Compared to fab and design costs,
everything else is nearly a rounding error.

Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)

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