[coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)
Stefan Roese
sr at denx.de
Thu Nov 2 15:10:31 CET 2017
Hi,
I'm facing a PCIe init related problem most likely caused in the
Intel FSP in our BayTrail U-Boot port (not coreboot!). I hope you
don't mind me posting this question on this coreboot list, since
here many more people are present with Intel FSP knowledge.
So here we go:
We are currently struggling with an FSP PCIe related issue on our
BayTrail target. Here we use an PLX / Avago PCIe switch, connected
to the PCIe root port of the CPU with a PCIe x4 link.
The BIOS always boots fine. Only U-Boot doesn't boot at all. No
output on the console. This is on some boards, somehow depending
on the PLX switch that is connected.
Measuring has shown, that the PCIe clock is only stable for ~20ms
before data is transferred in the U-Boot case. In the BIOS case,
the time between clock stable and data is ~120ms. The PCIe spec
mentions, that the clock should be asserted for more than 100ms.
So U-Boot is violating the spec here, which might be the root cause.
I've now instrumented the U-Boot with many early debug and delay
code and found, that it hangs inside of the FSP code. I then
installed the DEBUG FSP blob and have found, that its stuck (as
expected) in the FSP PCIe init:
....
CommonUsbInit() - End
ConfigureUsb() End
PchInitRootPorts() Start
Here the log from a different board, with stable and working
4 times x1 PCIe links (different board with 4 times x1 PCIe
links -> pci-good):
...
CommonUsbInit() - End
ConfigureUsb() End
PchInitRootPorts() Start
Root Port 1 device enabled. RpEnableMask: 0xF
Root Port 2 device enabled. RpEnableMask: 0xF
Root Port 3 device enabled. RpEnableMask: 0xF
Root Port 4 device enabled. RpEnableMask: 0xF
PchInitRootPorts() End
ConfigureSata() Start
...
I've attached the logs, so that you can review them yourself
as well.
Do you have any ideas, whats going on in the PCI init stuff in the
FSP? Or if and how we can influence this PCIe related configuration
to solve this hangup inside of the FSP? Has such a problem or a
similar one been noticed on some BayTrail platforms with coreboot
before?
BTW:
I've just found a workaround (more ugly hack) to solve this issue.
If I disable the link in the PCIe root port (PCI BDF 0,0x1c,0)
in the LCTL register before jumping into the FSP, the FSP
"survives" the init phase and jumps back into U-Boot. I can
then re-force the link before the U-Boot PCI scan is done
and then everything is fine. The PCIe PLX switch is detected
correctly and all downstream ports seem to be working as
expected.
Thanks,
Stefan
-------------- next part --------------
<test4>
============= PEIM FSP (VLYVIEW0 0x00000304) =============
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389
Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4
The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000
Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926
PcdMrcInitTsegSize = 1
PcdMrcInitMmioSize = 800
PcdMrcInitSPDAddr1 = A0
PcdMrcInitSPDAddr2 = A2
Setting BootMode to 0
Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
About to call MrcInit();
BayleyBay Platform Type
RID = 0x11.
Reg_EFF_DualCH_EN = 0x100301C0.
CurrentMrcData.BootMode = 4
Configuring Memory Start...
Configuring Memory End
UpperTotalMemory = 0x100000000
dBMBOUND = 0x80000000
dBMBOUNDHI = 0x180000000
dGFXBase = 0x7BE00000
dTSegBase = 0x7BD00000
Save MRC params.
Current MRC Data DDR Freq 2
Current MRC Data Core Freq 2
Current MRC Data Tcl 8
Current MRC Data WL 7
Current MRC Data DDRType 1
Current MRC Data MMIO Size 800
Current MRC Data TSeg Size 1
Channel 0
Enabled 1
Socket 0
DimmPresent 1
DimmDataWidth 1
DimmBusWidth 3
DimmSize 2
DimmSides 0
Channel 1
Enabled 1
Socket 0
DimmPresent 1
DimmDataWidth 1
DimmBusWidth 3
DimmSize 2
DimmSides 0
Current MRC Timing Data MRC_DATA_TRP 8
Current MRC Timing Data MRC_DATA_TRCD 8
Current MRC Timing Data MRC_DATA_TRAS 18
Current MRC Timing Data MRC_DATA_TWR 8
Current MRC Timing Data MRC_DATA_TWTR 4
Current MRC Timing Data MRC_DATA_TRRD 6
Current MRC Timing Data MRC_DATA_TRTP 4
Current MRC Timing Data MRC_DATA_TFAW 16
PeiInstallPeiMemory MemoryBegin 0x7B600000, MemoryLength 0x200000
Old Stack size 24576, New stack size 131072
Heap Offset = 0x0 Stack Offset = 0x838F0000
Stack Hob: BaseAddress=0x7B600000 Length=0x20000
Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281
Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F
InstallVlvInitPpi() - Start
Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3
InstallVlvInitPpi() - End
InstallPchInitPpi() - Start
PmcBase needs to be programmed and enabled before here.
ProgramGpioSCForSDCardWA Done....
Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D
Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7B7CB3C4
PchModPhyProgramming() - Start
SOC B0 and later ModPhy Table programming
PchModPhyProgramming() - End
PchSataInit() - Start
PchSataInit() - End
InstallPchInitPpi() - End
Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6
Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5
Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C
Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3
Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7B7DE2E9
VlvInitPeiEntryPoint start....
------------------------ VLV SSA Platform Policy dump Begin ---------------
Graphics Configuration:
GttSize : 2 MB
IgdDvmt50PreAlloc : 2
PrimaryDisplay : 0
ApertureSize : 2
Turbo Enable : 1
------------------------ VLV SSA Platform Policy dump END -----------------
ProgramEcBase Done....
SSASafeConfiguration Done....
Clear Dbuff to all zero before read 0xFFFFFFFF
PUNIT_ISPSSPM0 value is 0x3000003
ISP Device is enabled by fuse
Skip ISPConfig
InitThermalRegisters Done....
IGD enabled.
IGD Turbo Enable.
PUNIT_BIOS_CONFIG11 = 0x100301C0.
PUNIT_BIOS_CONFIG22 = 0x10030140.
TotalMmioLength: 0x10400000 bytes
GraphicsInit Done....
Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11
Install mVlvPeiInitPpi Done....
Install PPI: 15344673-D365-4BE2-8513-1497CC07611D
Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7B7CBB94
PchInitialize() - Start
PchMiscInit() - Start
PchMiscInit() - End
PchIoApicInit() - Start
PchIoApicInit() - End
PchPeimEhciPllCfg() SystemConfiguration->EhciPllCfgEnable = 0x0
PchInitialize() - End
Install PPI: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6
Notify: PPI Guid: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6, Peim notify entry point: 7B7C02D1
Initializing GT PowerManagement and other GT POST related
Initializing GT PowerManagement
Polling allow-wake bit
Polling Render Force Wake Acknowledge Bit
Polling Media ForceWakeReq Acknowledge Bit
PcBase = 0x7FEFA000
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Install PPI: F8BFF014-18FB-4EF9-B10C-AE22738DBEED
Auto Detect: B0 and later: SCC eMMC 4.5 Configuration
ConfigureSoCGpio------------start
ConfigureSoCGpio------------end
ConfigureLpssAndSccGpio------------start
ConfigureLpssAndSccGpio------------end
PchInitInterrupt () - Start
PchInitInterrupt () - End
ConfigureLpeGpio------------start
ConfigureLpeGpio------------end
Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5
Notify: PPI Guid: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5, Peim notify entry point: 7B7972D0
PchInitEntryPoint() Start
PCH Base Addresses:
-------------------
RCBA 0xFED1C000
PmcBase 0xFED03000
IoBase 0xFED0C000
IlbBase 0xFED08000
SpiBase 0xFED01000
MphyBase 0xFEF00000
AcpiBase 0x400
GpioBase 0x500
-------------------
InitializePchDevice() Start
ConfigureMiscPm() Start
ConfigureMiscPm() End
ConfigureAdditionalPm() PchPlatformPolicy->EhciPllCfgEnable = 0x0
ConfigureMiscItems() Start
ConfigureMiscItems() End
ConfigureAzalia() Start
Skip Azalia Codec detection.
Putting Azalia Controller into D3 Hot State.
AzaliaEnable = 0
ConfigureOtg() Start
USB3 OTG not present, skipping.
ConfigureOtg() End
ConfigureUsb() Start
CommonUsbInit() - Start
B2 or B2+ SOC on BayleyBay RVP
USB2_PHY USB2_COMPBG:0x4700
USB2PHY reg(0x4100): 0x49A09
USB2PHY reg(0x4122): 0x300401D
USB2PHY reg(0x4200): 0x49A09
USB2PHY reg(0x4222): 0x300401D
USB2PHY reg(0x4300): 0x49209
USB2PHY reg(0x4322): 0x1004015
USB2PHY reg(0x4400): 0x49A09
USB2PHY reg(0x4422): 0x300401D
CCU DIV_CTRL value ->0x3A08, cr_ush_clk_sel bit is 0x0
B2 or B2+ SOC on BayleyBay RVP
USB2_PHY USB2_COMPBG:0x4700
USB2PHY reg(0x4100): 0x49A09
USB2PHY reg(0x4122): 0x300401D
USB2PHY reg(0x4200): 0x49A09
USB2PHY reg(0x4222): 0x300401D
USB2PHY reg(0x4300): 0x49209
USB2PHY reg(0x4322): 0x1004015
USB2PHY reg(0x4400): 0x49A09
USB2PHY reg(0x4422): 0x300401D
set Late FID Check Disable:0x501037F
UsbXhciLpmSupport enabled-->XhciM mioBase:0x-257949696
CDN_PHY R_PCH_CDN_PLL_CONTROL:0x73
CDN_PHY R_PCH_CDN_VCO_START_CALIBRATION_START_POINT:0xA
Ccdrlf_configuration:0x1D46018B
ree_peaking_amp_configuration_and_diagnostic :0x1FF
ree_offset_correction_configuration_and_diagnostics:0x0
ree_vga_gain_configuration_and_diagnostics.:0x2F
ree_dac_control.:0x249F0006
CDN_PHY R_PCH_CDN_U1_POWER_STATE_DEFINITION:0x1BCF
Putting EHCI into D3 Hot State.
CommonUsbInit() - End
ConfigureUsb() End
PchInitRootPorts() Start
Root Port 1 device enabled. RpEnableMask: 0xF
Root Port 2 device enabled. RpEnableMask: 0xF
Root Port 3 device enabled. RpEnableMask: 0xF
Root Port 4 device enabled. RpEnableMask: 0xF
PchInitRootPorts() End
ConfigureSata() Start
ConfigureSata() End
ConfigureLpe() Start
ConfigureLpe() End
ConfigureLpss() Start
Putting LPSS2 DMA into D3 Hot State.
Putting LPSS2 I2C 0 into D3 Hot State.
LpssPciMmBase:------------------E00C1000.
Putting LPSS2 I2C 1 into D3 Hot State.
Putting LPSS2 I2C 2 into D3 Hot State.
Putting LPSS2 I2C 3 into D3 Hot State.
Putting LPSS2 I2C 4 into D3 Hot State.
Putting LPSS2 I2C 5 into D3 Hot State.
Putting LPSS2 I2C 6 into D3 Hot State.
Putting LPSS1 HS-UART 0 into D3 Hot State.
ConfigureLpss() End
ConfigureScc() Start
eMMC DLL Settings for BBAY.
ConfigureDLLSettingForEMMC45: eMMC DLL Settings for BayleyBay .
Putting SCC eMMC 4.41 into D3 Hot State.
Disable Transfer Suspend/Resume support for SOC B0 and later!
ConfigureSdCardCap: Overwride Capability Register
ConfigureSdCardCap: New Capability Reg = 0x80000000-76864B2
Enable 2ms_card_stable feature for B1 and later SOC!
ConfigureEMMC45: Overwride Capability Register
ConfigureEMMC45: New Capability Reg = 0x80000005-446CC801
ConfigureScc() End
ConfigureClockGating() Start
ConfigureClockGating() End
ConfigureIoApic() Start
ConfigureIoApic() End
ProgramSvidSid() Start
Writing SVID/SID for B0/D31/F3
Writing SVID/SID for B0/D31/F0
Writing SVID/SID for B0/D30/F5
Writing SVID/SID for B0/D30/F4
Writing SVID/SID for B0/D30/F2
Writing SVID/SID for B0/D30/F1
Writing SVID/SID for B0/D30/F0
Writing SVID/SID for B0/D28/F3
Writing SVID/SID for B0/D28/F2
Writing SVID/SID for B0/D28/F1
Writing SVID/SID for B0/D28/F0
Writing SVID/SID for B0/D2/F0
Writing SVID/SID for B0/D23/F0
Writing SVID/SID for B0/D21/F0
Writing SVID/SID for B0/D20/F0
Writing SVID/SID for B0/D19/F0
Writing SVID/SID for B0/D18/F0
Writing SVID/SID for B0/D17/F0
ProgramSvidSid() End
InitializePchDevice() End
Install PPI: D31F0400-7D16-4316-BF88-6065883B402B
PchInitEntryPoint() End
Detected Boot Mode 0
Detected 4 CPU threads
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
DXE IPL Entry
FSP HOB is located at 0x7B620000
FSP is waiting for NOTIFY
<debug_uart> <starting loop...>
<...loop finished>
<test1>
<debug_uart> <starting loop...>
<...loop finished>
<debug_uart> <starting loop...>
<...loop finished>
<test24>
<test27>
<test28>
U-Boot 2017.09-00063-g522351a8d9-dirty (Oct 20 2017 - 14:24:06 +0200)
CPU: x86_64, vendor Intel, device 30679h
DRAM: 4 GiB
pci_uclass_child_post_bind (925)
pci_uclass_pre_probe, bus=0/pci, parent=root_driver
decode_regions: len=18, cells_per_record=6
decode_regions: region 0, pci_addr=80000000, addr=80000000, size=40000000, space_code=2
- type=0, pos=0
decode_regions: region 1, pci_addr=c0000000, addr=c0000000, size=20000000, space_code=2
- type=8, pos=1
decode_regions: region 2, pci_addr=2000, addr=2000, size=e000, space_code=1
- type=1, pos=2
pci_uclass_pre_probe (865): LCTL=ffffffff
pci_uclass_pre_probe (875): LCTL=ffffffff
pci_uclass_post_probe: probing bus 0
pci_bind_bus_devices: bus 0/pci: found device 0, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f00
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_bind_bus_devices: bus 0/pci: found device 2, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f31
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: Match found: vesa_video
pci_bind_bus_devices: bus 0/pci: found device 11, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f15
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: Match found: pci_mmc
pci_bind_bus_devices: bus 0/pci: found device 12, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f16
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: Match found: pci_mmc
pci_bind_bus_devices: bus 0/pci: found device 13, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f23
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: Match found: ahci_pci
pci_bind_bus_devices: bus 0/pci: found device 14, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f35
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: Match found: xhci_pci
pci_bind_bus_devices: bus 0/pci: found device 15, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f28
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_bind_bus_devices: bus 0/pci: found device 17, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f50
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: Match found: pci_mmc
pci_bind_bus_devices: bus 0/pci: found device 1c, function 0
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f48
pci_uclass_child_post_bind (925)
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_bind_bus_devices: bus 0/pci: found device 1c, function 1
pci_find_and_bind_driver: Searching for driver: vendor=8086, device=f4a
-------------- next part --------------
<test4>
============= PEIM FSP (VLYVIEW0 0x00000304) =============
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389
Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4
The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000
Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926
PcdMrcInitTsegSize = 1
PcdMrcInitMmioSize = 800
PcdMrcInitSPDAddr1 = A0
PcdMrcInitSPDAddr2 = A2
Setting BootMode to 0
Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
About to call MrcInit();
BayleyBay Platform Type
RID = 0x11.
Reg_EFF_DualCH_EN = 0x100301C0.
CurrentMrcData.BootMode = 4
Configuring Memory Start...
Configuring Memory End
UpperTotalMemory = 0x100000000
dBMBOUND = 0x80000000
dBMBOUNDHI = 0x180000000
dGFXBase = 0x7BE00000
dTSegBase = 0x7BD00000
Save MRC params.
Current MRC Data DDR Freq 2
Current MRC Data Core Freq 2
Current MRC Data Tcl 8
Current MRC Data WL 7
Current MRC Data DDRType 1
Current MRC Data MMIO Size 800
Current MRC Data TSeg Size 1
Channel 0
Enabled 1
Socket 0
DimmPresent 1
DimmDataWidth 1
DimmBusWidth 3
DimmSize 2
DimmSides 0
Channel 1
Enabled 1
Socket 0
DimmPresent 1
DimmDataWidth 1
DimmBusWidth 3
DimmSize 2
DimmSides 0
Current MRC Timing Data MRC_DATA_TRP 8
Current MRC Timing Data MRC_DATA_TRCD 8
Current MRC Timing Data MRC_DATA_TRAS 18
Current MRC Timing Data MRC_DATA_TWR 8
Current MRC Timing Data MRC_DATA_TWTR 4
Current MRC Timing Data MRC_DATA_TRRD 6
Current MRC Timing Data MRC_DATA_TRTP 4
Current MRC Timing Data MRC_DATA_TFAW 16
PeiInstallPeiMemory MemoryBegin 0x7B600000, MemoryLength 0x200000
Old Stack size 24576, New stack size 131072
Heap Offset = 0x0 Stack Offset = 0x838F0000
Stack Hob: BaseAddress=0x7B600000 Length=0x20000
Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281
Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F
InstallVlvInitPpi() - Start
Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3
InstallVlvInitPpi() - End
InstallPchInitPpi() - Start
PmcBase needs to be programmed and enabled before here.
ProgramGpioSCForSDCardWA Done....
Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D
Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7B7CB3C4
PchModPhyProgramming() - Start
SOC B0 and later ModPhy Table programming
PchModPhyProgramming() - End
PchSataInit() - Start
PchSataInit() - End
InstallPchInitPpi() - End
Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6
Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5
Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C
Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3
Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7B7DE2E9
VlvInitPeiEntryPoint start....
------------------------ VLV SSA Platform Policy dump Begin ---------------
Graphics Configuration:
GttSize : 2 MB
IgdDvmt50PreAlloc : 2
PrimaryDisplay : 0
ApertureSize : 2
Turbo Enable : 1
------------------------ VLV SSA Platform Policy dump END -----------------
ProgramEcBase Done....
SSASafeConfiguration Done....
Clear Dbuff to all zero before read 0xFFFFFFFF
PUNIT_ISPSSPM0 value is 0x3000003
ISP Device is enabled by fuse
Skip ISPConfig
InitThermalRegisters Done....
IGD enabled.
IGD Turbo Enable.
PUNIT_BIOS_CONFIG11 = 0x100301C0.
PUNIT_BIOS_CONFIG22 = 0x10030140.
TotalMmioLength: 0x10400000 bytes
GraphicsInit Done....
Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11
Install mVlvPeiInitPpi Done....
Install PPI: 15344673-D365-4BE2-8513-1497CC07611D
Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7B7CBB94
PchInitialize() - Start
PchMiscInit() - Start
PchMiscInit() - End
PchIoApicInit() - Start
PchIoApicInit() - End
PchPeimEhciPllCfg() SystemConfiguration->EhciPllCfgEnable = 0x0
PchInitialize() - End
Install PPI: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6
Notify: PPI Guid: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6, Peim notify entry point: 7B7C02D1
Initializing GT PowerManagement and other GT POST related
Initializing GT PowerManagement
Polling allow-wake bit
Polling Render Force Wake Acknowledge Bit
Polling Media ForceWakeReq Acknowledge Bit
PcBase = 0x7FEFA000
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Install PPI: F8BFF014-18FB-4EF9-B10C-AE22738DBEED
Auto Detect: B0 and later: SCC eMMC 4.5 Configuration
ConfigureSoCGpio------------start
ConfigureSoCGpio------------end
ConfigureLpssAndSccGpio------------start
ConfigureLpssAndSccGpio------------end
PchInitInterrupt () - Start
PchInitInterrupt () - End
ConfigureLpeGpio------------start
ConfigureLpeGpio------------end
Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5
Notify: PPI Guid: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5, Peim notify entry point: 7B7972D0
PchInitEntryPoint() Start
PCH Base Addresses:
-------------------
RCBA 0xFED1C000
PmcBase 0xFED03000
IoBase 0xFED0C000
IlbBase 0xFED08000
SpiBase 0xFED01000
MphyBase 0xFEF00000
AcpiBase 0x400
GpioBase 0x500
-------------------
InitializePchDevice() Start
ConfigureMiscPm() Start
ConfigureMiscPm() End
ConfigureAdditionalPm() PchPlatformPolicy->EhciPllCfgEnable = 0x0
ConfigureMiscItems() Start
ConfigureMiscItems() End
ConfigureAzalia() Start
Skip Azalia Codec detection.
Putting Azalia Controller into D3 Hot State.
AzaliaEnable = 0
ConfigureOtg() Start
USB3 OTG not present, skipping.
ConfigureOtg() End
ConfigureUsb() Start
CommonUsbInit() - Start
B2 or B2+ SOC on BayleyBay RVP
USB2_PHY USB2_COMPBG:0x4700
USB2PHY reg(0x4100): 0x49A09
USB2PHY reg(0x4122): 0x300401D
USB2PHY reg(0x4200): 0x49A09
USB2PHY reg(0x4222): 0x300401D
USB2PHY reg(0x4300): 0x49209
USB2PHY reg(0x4322): 0x1004015
USB2PHY reg(0x4400): 0x49A09
USB2PHY reg(0x4422): 0x300401D
CCU DIV_CTRL value ->0x3A08, cr_ush_clk_sel bit is 0x0
B2 or B2+ SOC on BayleyBay RVP
USB2_PHY USB2_COMPBG:0x4700
USB2PHY reg(0x4100): 0x49A09
USB2PHY reg(0x4122): 0x300401D
USB2PHY reg(0x4200): 0x49A09
USB2PHY reg(0x4222): 0x300401D
USB2PHY reg(0x4300): 0x49209
USB2PHY reg(0x4322): 0x1004015
USB2PHY reg(0x4400): 0x49A09
USB2PHY reg(0x4422): 0x300401D
set Late FID Check Disable:0x501037F
UsbXhciLpmSupport enabled-->XhciM mioBase:0x-257949696
CDN_PHY R_PCH_CDN_PLL_CONTROL:0x73
CDN_PHY R_PCH_CDN_VCO_START_CALIBRATION_START_POINT:0xA
Ccdrlf_configuration:0x1D46018B
ree_peaking_amp_configuration_and_diagnostic :0x1FF
ree_offset_correction_configuration_and_diagnostics:0x0
ree_vga_gain_configuration_and_diagnostics.:0x2F
ree_dac_control.:0x249F0006
CDN_PHY R_PCH_CDN_U1_POWER_STATE_DEFINITION:0x1BCF
Putting EHCI into D3 Hot State.
CommonUsbInit() - End
ConfigureUsb() End
PchInitRootPorts() Start
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