[coreboot] Problems changing payload on Intel Leaf Hill

Scheithauer, Mario Mario.Scheithauer at siemens.com
Thu Nov 2 10:18:03 CET 2017

Hi Kevin,

Yes, we had to make another adjustment.
I think SeaBios is expecting a pointer at this position to the beginning of the CBFS.
But coreboot doesn't enter anything there, because everything works over the FMAP.
But it may also be that we are still doing something wrong.

-> CONFIG_CBFS_LOCATION = top of memory (0xFFFFFFFF) - SPI Flash size + CBFS end position (FMAP) + DEVICE_EXTENSION size (FMAP) + UNUSED_HOLE size (FMAP)
-> At this position there is only 0xffffffff and SeaBios has a problem with that.
-> 0xff401838 = top of memory (0xFFFFFFFF) - SPI Flash size + DEVICE_EXTENSION size (FMAP) + UNUSED_HOLE size (FMAP) + CBFS master header size (0x38)
-> It all depends on the FMAP
-> If we put into the pointer there, SeaBios will also find the CBFS and everything is fine


> -----Ursprüngliche Nachricht-----
> Von: Kevin O'Connor [mailto:kevin at koconnor.net]
> Gesendet: Donnerstag, 2. November 2017 00:45
> An: Scheithauer, Mario (DF MC MTS R&D SWRT 4)
> Cc: Tahnia Lichtenstein; coreboot at coreboot.org
> Betreff: Re: [coreboot] Problems changing payload on Intel Leaf Hill
> On Wed, Nov 01, 2017 at 03:28:45PM +0000, Scheithauer, Mario wrote:
> > Hi Tahnia,
> >
> > We have an APL CRB Oxbow Hill (B0-stepping) with coreboot (master) +
> SeaBios (master) running.
> > Attached are all necessary coreboot adaptions and the config file for SeaBios.
> > After the generation, a hack in coreboot.rom is still necessary so that SeaBios can
> find the VBIOS.
> > SeaBios expects at the end of the CBFS the address from the beginning of the
> CBFS section (see SeaBiosPointer.jpg).
> When you say "a hack in coreboot.rom", are you referring to the
> CONFIG_CBFS_LOCATION=0xfff9f000 seabios setting or was some additional
> change necessary?
> -Kevin

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