[coreboot] Remote security exploit in all 2008+ Intel platforms

[ron minnich]

On Mon, May 1, 2017 at 2:54 PM Raphael Jacquot <sxpert at sxpert.org> wrote:

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> what kind of performance can be expected from RiscV ?
>
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Performance is not the issue. The issue is when it will be ready, and in a
laptop you like, and the answer is "not for a while".

Further, while the RISCV instruction set and architecture are open source,
that really doesn't imply that  things such as SMM can't be implemented on
them. RISC-V M mode will allow such things in fact. I failed to convince
the RISCV community that M-mode code should be part of the kernel, in the
hopes of making it impossible to have something like SMM. I failed.

Don't assume, just because the instruction set is open source, that all the
problems go away. They don't. System vendors can still do a lot.
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