[coreboot] SPI Flash does not work on Intel LeafHill CRB

Aaron Durbin adurbin at google.com
Thu Mar 30 16:15:02 CEST 2017

On Thu, Mar 30, 2017 at 4:53 AM, Goetz Salzmann <ml-coreboot at blacknet.de> wrote:
> Dear Toan,
>> I tried as your suggestion: flashed an 8 MB Intel-provided image, read
>> back from SPI chip right after flashing, got a 16 MB file (since SPI
>> chip is 16 MB size).
>> The first 8 MB of 2 files are exactly the same. So, flashing should
>> work fine.
> that's your problem right there.  The last 128kB of the SPI flash will be
> mapped to the End ot 1MB, there the CPU will start executing.  In your
> case, that's not the IBB / coreboot, but zeros (ok, maybe 0xFFs).

That's not exactly true. What is mapped below 4GiB in CPU address
space is the BIOS region described in the firmware descriptor. That
can float within the SPI address space. i.e. it doesn't have to be at
the end. To complicate matters further the IBBL on apollolake is found
in the IFWI -- completely separate from the CBFS and coreboot side of
things. The ifiwitool jams the bootblock into the right place. Lastly,
if there's not a correct setting applied in the descriptor the CSE
validates and checks that there are 2 IFWIs -- one is primary and one
is secondary. The secondary has to live directly at halfway point of
BIOS region (not half of SPI itself) with a 4KiB alignment, iirc.

> You have to rebuild your image for the correct flash size.
> Have fun,
>     Goetz.
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