[coreboot] riscv: How to debug (王翔)
j.neuschaefer at gmx.net
Fri Jun 9 18:50:35 CEST 2017
On Fri, Jun 09, 2017 at 12:47:59PM +0800, 王翔 wrote:
> On Friday,June 9, 2017 at 12:34 PM,王翔 wrote:
> >I get source frome https://github.com/riscv/riscv-tools.git.
> >Compare the difference with https://github.com/riscv/riscv-isa-sim/pull/53 and fix the code.
> >The difference of Our patch is **UART_BASE**. You use 0x02100000, me use 0x40001000.
> >In my test 0x40001000 can be work with **coreboot**, but 0x02100000 can not.
> >My patch is in the attachment of the message.
> I'm sorry. I not change **uintptr_t uart_platform_base(int idx)**
I've updated https://github.com/riscv/riscv-isa-sim/pull/53 and uploaded
a coreboot patch to use the new UART address¹:
> >>What did you test? How did it fail?
> >I test by **spike**. I have report the patch.
> But these bugs still exist.
Thank you for these patches.
¹) It wasn't strictly necessary to change the UART address, but I think
0x02100000 fits better into the current address map.
The old patch is available at
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