[coreboot] riscv: How to debug

Jonathan Neuschäfer j.neuschaefer at gmx.net
Fri Jun 9 03:17:11 CEST 2017

On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote:
> I try to debug coreboot with **spike**. 
> I has apply the **8250 usart patch** to **spike**.

I haven't updated the patches at [1] in a while. Please check if the two
patches in [2] work for you if you also apply the following patch to

diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c
index 57647fee1d..26ab630091 100644
--- a/src/mainboard/emulation/spike-riscv/uart.c
+++ b/src/mainboard/emulation/spike-riscv/uart.c
@@ -20,5 +20,5 @@
 uintptr_t uart_platform_base(int idx)
-	return (uintptr_t) 0x40001000;
+	return (uintptr_t) 0x02100000;

[1]: https://github.com/riscv/riscv-isa-sim/pull/53
[2]: https://github.com/neuschaefer/riscv-isa-sim/commits/uart-update

> But I get from the official website of the code can not pass the test.
> I found some BUG when I debug this.

What did you test? How did it fail?

Jonathan Neuschäfer
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