[coreboot] Coreboot at Apollo Lake Oxbohill CRB

[Zoran Stojsavljevic]

> I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about

> the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know

> how to create required FSP blob from FSP.bsf and FSP.fd files?

FSP-M: MRC code

FSP-S: Silicon init code

> I have built coreboot image for Apollo Lake and trying to boot Oxbohill CRB but no console or display at HDMI port.

Good Luck with your build! ;-)

Zoran

PS. Tiho, Andrei. Potihon6ky, ponjatno. Esli M(R)C zametit6 tebja,
koecto mozet slucitsja, esli on tebja (prezde vsego) NE pozvolil
hozjataistvovat6 zdes6. ;-)

Elki Palki (Kopalki)!

Udaci! Zoran


On Sat, Feb 25, 2017 at 11:48 AM, Gailu Singh <gailu96 at gmail.com> wrote:

> >>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp.
>
> >>Please use https://review.coreboot.org/#/c/18479/3 as starting point.
> >>That is for Leafhill. But once you apply that patch, select mainboard
> >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated
> >>location and 'make' should give you flashable coreboot.rom.
>
>
> I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know how to create required FSP blob from FSP.bsf and FSP.fd files?
>
>
>
> On Sat, Feb 25, 2017 at 10:49 AM, Gailu Singh <gailu96 at gmail.com> wrote:
>
>> Hi Experts,
>>
>> I have built coreboot image for Apollo Lake and trying to boot Oxbohill
>> CRB but no console or display at HDMI port.
>>
>> My coreboot.rom details
>>
>> Name                           Offset     Type         Size
>> cbfs master header             0x0        cbfs header  32
>> fallback/romstage              0x80       stage        28268
>> cpu_microcode_blob.bin         0x6f40     microcode    0
>> fallback/ramstage              0x6fc0     stage        65343
>> config                         0x16f40    raw          291
>> revision                       0x170c0    raw          569
>> fallback/postcar               0x17340    stage        16916
>> fallback/dsdt.aml              0x1b5c0    raw          99
>> fallback/payload               0x1b680    payload      361265
>> (empty)                        0x73a00    null         443544
>> mrc.cache                      0xdfec0    mrc_cache    65536
>> (empty)                        0xeff00    null         32664
>> bootblock                      0xf7ec0    bootblock    32768
>>
>> This is an 8 MB image, I flashed it to SPI flash at address 0. When I
>> boot the board no output is observed either on USB serial console or on
>> HDMI display.
>>
>> Do I need to add something more to see at least coreboot log. I am tryng
>> to use GRUB2 as payload to coreboot.
>>
>> Thanks
>>
>>
>
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