[coreboot] Back to original BIOS

Zoran Stojsavljevic zoran.stojsavljevic at gmail.com
Sun Feb 5 18:00:21 CET 2017


Hello Michael,

Before doing any programming, I have here couple suggestions to you. You
should investigate.

Namely, this: http://thinkwiki.de/UEFI_BIOS_T420_BIOS_Structure

Also, you should look upon the movie here:
https://www.youtube.com/watch?v=DLwaKb6pLrc&feature=player_embedded

Since I am not sure that T420 UEFI BIOS is the same structure as legacy
BIOS T400 has (since I remember that T420 is UEFI, legacy/CSM was on - I
had one at work since 2011 till 2014). But it is worth trying, nothing to
lose.

Knowing that T420 BIOS structure looks like (and I bet it is stored in only
one 8MB flash, as my best bet):

[image: Inline image 1]

You should read your T400 Coreboot flash content, and try to see if it
complies with the given above structure. If it does, you are All Cool.
Namely, you should try to read GbE region, and see where the MAC address
(which you find using Linux command: ifconfig -a). If you appear to find
the spot, you are 100% sure you are All Good, since then you'll read
another BIOS content, and after you will have lot of possibilities for
experiments:
[1] You can reprogram the BIOS from original BIOS to your Coreboot flash
rewriting last 0x300000 bytes;
[2] You can rewrite original MAC address to another BIOS, and try to boot;
[3] You can compare/combine regions, and see what'll happen?!
[4] You name it!

I have no idea if you tampered with ME... And no idea if ME for each LENOVO
specimen keeps some unique data from/for the platform.

But I am eager to hear/read what did you find investigating about T400
structure, does it looks the same as T420, and et cetera. :-)

You can also read descriptor region, and post it somewhere, so we can peek
into it (I remember, I have somewhere some explanations about some of these
descriptor region data).

Thank you,
Zoran

On Sat, Feb 4, 2017 at 8:41 AM, Michal Widlok <michalwd1979 at gmail.com>
wrote:

> Zoran, I'm working on this subject now, but I need to do regular work too
> :-).
>
> Seriously I'm in the process of changing my current stationary
> work-horse to two T400 laptops on docking stations. I've just received
> docks (very dirty, noisy fans) and I borrowed my Raspberry programmer
> to a friend. I hope to finish working on hardware this weekend and I
> will be ready to play with bioses when I get Raspberry back. I think
> that the first method would be to "copy" flash from one board to
> another and we will see. I also try to change MAC in original bios,
> maybe this is possible. I will report everything back, hope it will
> help someone.
> Michael Widlok
>
> PS. Sorry for double mail I messed addresses.
>
> On Fri, Feb 3, 2017 at 9:58 PM, Zoran Stojsavljevic
> <zoran.stojsavljevic at gmail.com> wrote:
> > Ron, I do agree, does not seem to be promising. It will add problems down
> > the road, as requirements grow.
> >
> > Zoran
> >
> > On Fri, Feb 3, 2017 at 8:45 PM, ron minnich <rminnich at gmail.com> wrote:
> >>
> >>
> >>
> >> On Fri, Feb 3, 2017 at 9:45 AM Zoran Stojsavljevic
> >> <zoran.stojsavljevic at gmail.com> wrote:
> >>>
> >>>
> >>>
> >>> Ron, any (practical) example of above described practices? I have in my
> >>> laptops here 6 x 4 GB DIMM modules and 2 x 8GB DIMM modules, all of
> them
> >>> have SPD mounted.
> >>
> >>
> >>
> >> DIMMs are so great but so old school :-)
> >>
> >> on some systems, in flash, there are 4 and 8 element tables which are
> >> indexed by GPIOs .You use the 2 or 3 bits from 2-3 GPIOs to index the
> table
> >> and that's how you get your RAM programming. No SPD. You can see how
> much
> >> room this leaves for problems.
> >>
> >> This is just one simple example.
> >>
> >> ron
> >>
> >
> >
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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