[coreboot] Doubt about SPD init in Skylake

[Nico Huber]

Hi,

On 30.12.2017 08:56, 王翔 wrote:
> The system must initialize some arrays before initializing the SPD in
> order to execute FspMemoryInit.  I do not know what these arrays do,
> and how do I get these values when porting new motherboard.
> 
> 
> These codes exist on the SKYLAKE platform which using FSP2.0.  Call path
> :
> fsp_memory_init->do_fsp_memory_init->platform_fsp_memory_init_params_cb->mainboard_memory_init_params
> 
> 
> array list : FSPM_UPD->FspmConfig->DqByteMapCh0
> FSPM_UPD->FspmConfig->DqByteMapCh1
> FSPM_UPD->FspmConfig->DqsMapCpu2DramCh0
> FSPM_UPD->FspmConfig->DqsMapCpu2DramCh1
> FSPM_UPD->FspmConfig->RcompResistor FSPM_UPD->FspmConfig->RcompTarget

These have nothing to do with the SPD information for your memory chips.
These settings are about board specific routing (and calibration, I
guess). The former four are only needed for soldered-down LPDDR3 memory,
AIUI, so if you have DIMMs with SPD they don't apply for your board.

The `RcompResistor` settings are chipset dependent. IIRC, you can find
these in the respective Platform Design Guide for your chipset. The
`RcompTarget` I've never really figured out. I can only guess, that this
is a board specific calibration target. You should ask your Intel con-
tacts about it.

For further assistance we'd need to know your exact target chipset (SKU)
and what kind of memory (e.g. DDR3/DDR4, DIMMs or soldered down) you use
on your board.

Hope that helps,
Nico