[coreboot] Skylake FSP 1.1 without verstage?

Trammell Hudson hudson at trmm.net
Wed Oct 5 22:08:12 CEST 2016

On Wed, Oct 05, 2016 at 01:59:08PM -0500, Aaron Durbin wrote:
> > Does the car stage code exist somewhere else in the tree?
> Try this? [...]
> -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
> +romstage-y += romstage_after_verstage.S

That works to make it past the romstage.  Now it crashes when it
loads the ramstage and tries to jump into it.  Progress!

> The transition to skylake using C_ENVIRONMENT_BOOTBLOCK looks to have
> broken this combination. I think the above should make things work for
> you.  Let me know.

It's better, although I'm still debugging.  Here is the console log
(this is using the fsp.bin and microcode blob extracted from the
chromebook firmware):

coreboot-4.4-1781-g2fcabb8-heads Wed Oct  5 01:45:23 UTC 2016 bootblock starting...
Calling FspTempRamInit
FspTempRamInit returned 0x00000000
CPU: Intel(R) Core(TM) m5-6Y57 CPU @ 1.10GHz
CPU: ID 406e3, Skylake D0, ucode: 00000089
CPU: AES supported, TXT supported, VT supported
MCH: device id 190c (rev 08) is Skylake-Y
PCH: device id 9d46 (rev 21) is Skylake-Y Premium
IGD: device id 191e (rev 07) is Skylake ULX GT2
CPU: frequency set to 1100 MHz
CBFS: 'Master Header Locator' located CBFS at [a00100:ffffc0)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size aecc
src/arch/x86/boot.c:223: jumping to ffa00200

coreboot-4.4-1781-g2fcabb8-heads Wed Oct  5 01:45:23 UTC 2016 romstage starting...
CBFS: 'Master Header Locator' located CBFS at [a00100:ffffc0)
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 4dfec0 size 7a000
CBFS: 'Master Header Locator' located CBFS at [a00100:ffffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 411440 size 17800
microcode: sig=0x406e3 pf=0x80 revision=0x89
microcode: updated to revision 0x89 date=2016-04-06
Using FSP 1.1
FSP Signature: $SKLFSP$
FSP Header Version: 2
FSP Revision:
FSP Entry Points:
    0xffee0000: Image Base
    0xfff58ea3: TempRamInit
    0xfff58fec: FspInit
    0xfff59000: MemoryInit
    0xfff5900a: TempRamExit
    0xfff59014: SiliconInit
    0xfff58ff6: NotifyPhase
    0xfff5a000: Image End
PM1_STS:   0100
PM1_EN:    0000
PM1_CNT:   00001c00
TCO_STS:   0000 0000
GPE0_STS:  00000000 00000000 00000000 00000000
GPE0_EN:   00000000 00000000 00000000 00000000
GEN_PMCON: e0a40200 0000520a
GBLRST_CAUSE: 00000000 00000000
Previous Sleep State: S5
MLB: board version 4
Google Chrome set keyboard backlight: 0 status (0)
SPD index 1
CBFS: 'Master Header Locator' located CBFS at [a00100:ffffc0)
CBFS: Locating 'spd.bin'
CBFS: Found @ offset 3cd380 size 600
SPD: module type is LPDDR3
SPD: module part is K4E6E304EE-EGCF   
SPD: banks 8, ranks 2, rows 14, columns 11, density 4096 Mb
SPD: device width 16 bits, bus width 64 bits
SPD: module size is 4096 MB (per channel)
FMAP: Found "FLASH" version 1.1 at a00000.
FMAP: base = ff000000 size = 1000000 #areas = 3
No MRC cache found.
VPD Data: 0xfff0215c
UPD Data: 0xfff02198
Calling FspMemoryInit: 0xfff59000
    0x00000000: NvsBufferPtr
    0xfef034d8: RtBufferPtr
    0xfef03480: HobListPtr
FspMemoryInit returned 0x00000000
Reserving 0x0000000000200000 bytes for FSP
0x00800000: smm_size
0x7b000000: smm_base
0x7af00000: cbmem_top
IMD: root @ 7aeff000 254 entries.
IMD: root @ 7aefec00 62 entries.
External stage cache:
IMD: root @ 7b3ff000 254 entries.
IMD: root @ 7b3fec00 62 entries.
0x7acfe000: fsp_reserved_memory_area
MRC data at 7ad295a8 6256 bytes
Relocate MRC DATA from 7ad295a8 to 7ac7b000 (6256 bytes)
CBMEM entry for DIMM info: 0x7aefe8c0
2 DIMMs found
Calling FspTempRamExit API
FspTempRamExit returned successfully
CBFS: 'Master Header Locator' located CBFS at [a00100:ffffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset afc0 size 12e29
Decompressing stage fallback/ramstage @ 0x7abbffc0 (743408 bytes)
Loading module at 7abc0000/7abc0000 with entry 7abc0000. filesize: 0x28d88 memsize: 0xb57b0
Processing 2472 relocs. Offset value of 0x7aac0000
src/arch/x86/boot.c:223: jumping to 7abc0000

(and then it crashes)


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