[coreboot] Skylake FSP 1.1 without verstage?

[Aaron Durbin]

On Wed, Oct 5, 2016 at 1:20 PM, Trammell Hudson <hudson at trmm.net> wrote:
> On Skylake with no verstage and FSP 1.1 there is no car_stage_entry
> function, only a weak symbol with an infinite loop in
> src/arch/x86/assembly_entry.S, and as a result coreboot hangs after
> jumping into the romstage.
>
> There is one defined in src/soc/intel/skylake/romstage/car_stage.S,
> but this is only linked if FSP 2.0 is used.  The Chell chromebook
> appears to use FSP 1.1, so I don't have the FSP-S and FSP-M binaries.
>
> Does the car stage code exist somewhere else in the tree?
>


Try this?

diff --git a/src/drivers/intel/fsp1_1/Makefile.inc
b/src/drivers/intel/fsp1_1/Makefile.inc
index 4ea23f3..025b067 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -28,7 +28,7 @@ romstage-y += fsp_util.c
 romstage-y += hob.c
 romstage-y += raminit.c
 romstage-y += romstage.c
-romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
+romstage-y += romstage_after_verstage.S
 romstage-y += stack.c
 romstage-y += stage_cache.c


The transition to skylake using C_ENVIRONMENT_BOOTBLOCK looks to have
broken this combination. I think the above should make things work for
you.  Let me know.

> --
> Trammell
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot