[coreboot] More details about ram issues

Charlotte Plusplus pluspluscharlotte at gmail.com
Sat Nov 12 05:00:42 CET 2016


On Fri, Nov 11, 2016 at 5:37 PM, Nico Huber <nico.h at gmx.de> wrote:

> > The W520 does only have 1.5V DDR voltage. If it's stable with vendor
> > bios, it's not a DDR voltage problem at all.

Based on my reading of the block diagram and crossing that with a cpu
pinout and the cpu specs, I disagree.  The W520 indeed only support 1.5V,
if you mean 1.5V vs 1.3 "low voltage" DDR3L.

But SA_DIMM_VREFDQ is in direct control of the DDR3 voltage: "The step size
is 7.7 mV". So it supports 1.5V +- k*0.007V, with k being given by the XMP

In case this is not clear, on
Page 30 : "The processor memory controller has the capability of generating
the DDR3 Reference  Voltage (VREF) internally for both read (RDVREF) and
write (VREFDQ) operations. The generated VREF can be changed in small
steps, and an optimum VREF value is  determined for both during a cold boot
through advanced DDR3 training procedures in  order to provide the best
voltage and signal margins."

That seems to be a lot of evidence in the voltage not being an absolutely
fixed 1.500V. It is something more flexible!!!

> That's what sandybridge raminit does. Only XMP profiles with DDR
> > voltage of 1.5V are used. Profiles that do have other voltage
> > setting are ignored.
> Good to know, I already started worrying about your code just by reading
> emails. Should have looked in the code instead ;) my apologies.

Yes, in spd_xmp_decode_ddr3, profiles not using 1.5V are discarded. I
believe this is the problem. When I did a google image search of "cpuz
ddr3", the first few hits showed me 1.6V and 1.65V XMP profiles. So there
are quite a few of such profiles out there. I'm not alone.

At the moment, I do not have any better explaination as to why my ram is
not stable than XMP profiles being not followed.

Patrick said above:"I don't think that XMP is the problem. My guess is that
raminit doesn't  set all required registers to fine tune the memory
controller to get it stable."

Maybe it is the explanation, and XMP profiles are indeed not needed at all.
Maybe I am very wrong in my analysis.

At the moment, I would just like to have the ram on my W520 stable when it
operates within specifications (and I mean within a XMP profile), as I was
planning to use the W520  as my main laptop, and I can't :-(

I thought porting coreboot to the W520 would help me do that. These ram
issues are really bothering me. I can't have unstable RAM on my main
laptop. This is why I am extremely motivated to make it work.

I will be making more tests tonight. I included the patch #17389 your
posted today: nb/intel/sandybridge/raminit: Fix CAS Write Latency

I disabled all my SPD hardcoding, and only disabled the MRC cache, so that
I can alternate between normal and fallback to run more tests without

I have strictly no experience with coreboot and I'm learning on the go.
Your help in fixing the RAM issues would be greatly appreciated

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20161111/85ccd804/attachment-0001.html>

More information about the coreboot mailing list