[coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8

Zoran Stojsavljevic zoran.stojsavljevic at gmail.com
Sat May 21 09:25:56 CEST 2016


Hello Cheng,

There is some grief/catch 22 introduced while INTEL ported BYT FSP +
Coreboot upstream patches into real Coreboot (Coreboot 4.4 inherited these
patches from older Coreboot tree, my best guess).

You should contact INTEL FSP team (namely York), and ask him to redo and
again inspect the patches deltas.

Best Regards,
Zoran

On Fri, May 20, 2016 at 2:36 PM, cheng yichen <blessyichen at gmail.com> wrote:

> Hi Zoran
>
> Intel coreboot code + FSP + seabios1.91 in win8.1: All device is workable
> and no yellow mark in device manager.
>
> All lpss device is workable and no yellow mark in AMI UEFI BIOS.
>
> coreboot4.4 + FSP+seabios1.91 in win8.1: lpss device is shown yellow mark
> in device manager.
>
> Thank you
>
> 2016-05-20 15:49 GMT+08:00 Zoran Stojsavljevic <
> zoran.stojsavljevic at gmail.com>:
>
>> Hello Chang,
>>
>> Just replace these info in my latest email (regarding BYT FSP and
>> Coreboot). The later use case and questions remain the same.
>>
>> Thank you,
>> Zoran
>>
>>
>> On Fri, May 20, 2016 at 9:16 AM, cheng yichen <blessyichen at gmail.com>
>> wrote:
>>
>>> Hi Zoran
>>>
>>> Sorry for the information is not clear. The MR5 that I mean is intel
>>> release coreboot source code and FSP in intel web side. In the debug
>>> message I find the version is coreboot4.0.
>>>
>>> in my previous mail, the MR5 is included intel coreboot source code and
>>> FSP package.
>>>
>>> Thank you
>>>
>>> 2016-05-17 11:36 GMT+08:00 Zoran Stojsavljevic <
>>> zoran.stojsavljevic at gmail.com>:
>>>
>>>> Hello Cheng,
>>>>
>>>> I am afraid, I have no ideas anymore what could be wrong. But I have
>>>> for you one suggestion (path to resolution, maybe).
>>>>
>>>> No idea what you are using. In the sense BYT-FSP (MR5) -> Coreboot ->
>>>> (payload???). You either use SeaBIOS (CSM ON), or Tiano Core/EK2 (CSM OFF).
>>>>
>>>> I would suggest the following: since it depends what payload you use
>>>> because you would like to reuse your old HDD with WIN 8.1, to make test
>>>> very short (no need to install other HDD with WIN 8.1).
>>>>
>>>> Please, take real UEFI BIOS (for BYT-M N2807 it is Client Group 64bit
>>>> A093.R42 or later), and install it on some INTEL CRB (BayleyBay or
>>>> BakerSport) where you already have N2807. Then, in relations what payload
>>>> you are using, you need to set CSM ON or CSM OFF, to make work/reuse your
>>>> original HDD with WIN 8.1.
>>>>
>>>> Please, after you are able to bring your INTEL BYT-M CRB to WIN 8.1,
>>>> reboot, and again enter BIOS CMOS. There, under system setup/advanced
>>>> settings, you should be able to find southbridge setup, where one of the
>>>> options is LPSS.
>>>>
>>>> Please, experiment, with settings within LPSS mode (PCI and ACPI), and,
>>>> please, report here do you have the same as with BYT-FSP MR5 settings as
>>>> you use "pcdlpsssioenablepcimode" to "LPSS_PCI_MODE_DISABLE" and
>>>> "ENABLE/DEFAULT" (do you see the same behavior in WIN 8.1 device manager)?
>>>>
>>>> Thank you,
>>>> Zoran
>>>>
>>>> On Mon, May 16, 2016 at 2:06 PM, cheng yichen <blessyichen at gmail.com>
>>>> wrote:
>>>>
>>>>> Hi  Zoran
>>>>>
>>>>> Base on the version Baytrail_coreboot_MR5_Dec-21-2015(coreboot) that
>>>>> is released by Intel.
>>>>> In the coreboot(Intel released and defautle is acpi mode) I can
>>>>> install driver and device is workable in win8.
>>>>> I can see hs-uart controller in device manage and no yellow mark.
>>>>>
>>>>> In last coreboot source code. after I modify "pcdlpsssioenablepcimode"
>>>>> to "LPSS_PCI_MODE_DISABLE". Then the lpss device will be confgured to ACPI
>>>>> mode.
>>>>> but the hs-uart controller and I2C controller will shown yellow mark
>>>>> in win8 device manager.
>>>>> Because the main controller is not workable in win8. I don't check the
>>>>> sub-device device.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> 2016-05-16 17:16 GMT+08:00 Zoran Stojsavljevic <
>>>>> zoran.stojsavljevic at gmail.com>:
>>>>>
>>>>>> Hello Cheng,
>>>>>>
>>>>>> Again, I'll repeat my questions:
>>>>>> [1] Are you talking about BIOS, where you are enabling in LPSS ACPI
>>>>>> (disabling automatically PCI) mode?
>>>>>> [2] I need better explanation of your use case... Are you using BYT
>>>>>> MR4, then MR5, or instead MR4 BIOS, or...?
>>>>>> [3] For WIN8.1 you need to have the following:
>>>>>>       For BIOS to work (and get rid off these yellow triangles with
>>>>>> question marks):
>>>>>>       [A] ACPI mode in BIOS: South Cluster Configuration -> LPSS &
>>>>>> SCC Configuration -> LPSS LPSS & SCC
>>>>>>            Devices Mode -> Select "ACPI Mode";
>>>>>>       [B] The GPIO controller driver is/should be prerequisite for
>>>>>> HS-UART driver. There is a document named:
>>>>>>             Intel_Processor_Win8_IO_Drivers_Gold_MR1. You should ask
>>>>>> for it from INTEL support. If installed
>>>>>>             correctly, you should see HS-UART Controller device under
>>>>>> System Devices in Device Manager. Also
>>>>>>             new unknown devices should appear: ACPI\BCM2E1A and
>>>>>> ACPI\BCM4752. These devices are for
>>>>>>             HS-UART Sub Device Driver;
>>>>>>       [C] You should compile the UART Sub Device Driver (by 1.2.1 of
>>>>>> Intel Atom E3800 Win8.1 HS-UART Sub
>>>>>>             Device Driver Sample Code Guide_1.0), and install after
>>>>>> building them. After that you should see Ports in
>>>>>>             Device Manager.
>>>>>>
>>>>>> Zoran
>>>>>>
>>>>>> On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen at gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>>
>>>>>>> HI all
>>>>>>>
>>>>>>> I try to enable Lpss device(i2c hs-uart) with ACPI mdoe.
>>>>>>> i2c and hs-uart will show yellow mark in device manager with win8.1.
>>>>>>> but I can't find the same issue in intel coreboot(versrion MR5).
>>>>>>> Do you have any idea for the issue? Thank you
>>>>>>>
>>>>>>> --
>>>>>>> coreboot mailing list: coreboot at coreboot.org
>>>>>>> https://www.coreboot.org/mailman/listinfo/coreboot
>>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>> --
>>> coreboot mailing list: coreboot at coreboot.org
>>> https://www.coreboot.org/mailman/listinfo/coreboot
>>>
>>
>>
>
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