[coreboot] [regression] Increased romstage boot time on ASRock E350M1 (AMD Family 14h)

[Martin Roth]

I've been bisecting this today.  I see an increase of about 1 second
somewhere between commit 35261c0d476ef and commit 730a043fb6c.  That's
a range of 15 commits

On the good commits, I get the boot messages:
> APIC: 00 missing read_resources
> APIC: 01 missing read_resources
> I2C: 00:50 missing read_resources
> I2C: 00:51 missing read_resources
> Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
'> mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
> Payload not loaded.

On the bad commits, I get the boot messages:
> APIC: 00 missing read_resources
> APIC: 01 missing read_resources
> I2C: 00:50 missing read_resources
> I2C: 00:51 missing read_resources
> skipping PNP: 002e.307 at 23 fixed resource, size=0!
> skipping PNP: 002e.307 at e4 fixed resource, size=0!
> skipping PNP: 002e.307 at ed fixed resource, size=0!
> skipping PNP: 002e.9 at 2a fixed resource, size=0!
> skipping PNP: 002e.9 at e0 fixed resource, size=0!
> skipping PNP: 002e.a at e7 fixed resource, size=0!
> skipping PNP: 002e.d at ec fixed resource, size=0!
> Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
> 'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
> Payload not loaded.

I don't think that this has anything to do with system tools.   I can
continue bisecting tomorrow, but I expect that the extra time will be
found in one of these commits:

68825740 - asrock/e350m1: Add ACPI S3 support
d28474b4 - asrock/e350m1: Match super-io GPIO configuration with vendor
3b01cf17 - superio/nuvoton/nct5572d: Add missing logical devices

Martin