[coreboot] Using eMMC on Baytrail with FSP
gardner.ben at gmail.com
Thu Jan 14 18:36:32 CET 2016
I've been using eMMC with the baytrail FSP on the E3800 CPU without issue.
I don't recall doing anything special to get it to work under Linux.
Comparing my devicetree.cb with bayleybay_fsp shows these differences
related to eMMC.
I don't know if any of those are important.
register "PcdEMMC45DDR50Enabled" = "EMMC45_DDR50_DISABLE"
register "PcdEMMC45HS200Enabled" = "EMMC45_HS200_DISABLE"
register "PcdEMMC45RetuneTimerValue" = "EMMC45_RETURN_TIMER_DEFAULT"
I also have devices 0x11 and 0x12 turned off.
By "relevant" pins, I assume you mean GPIO_S0_SC thru GPIO_S0_SC.
On Wed, Jan 13, 2016 at 9:16 AM, David Popeck <david at justaride.org> wrote:
> Hi all,
> I've been trying to get Coreboot going on a custom Baytrail based board that
> I have.
> Pretty much everything is working with one major exception - eMMC.
> I've enabled eMMC in BCT.
> In devicetree.cb I've switched off device 10 (eMMC 4.1 controller) and
> switched on device 17 (eMMC 4.5 controller).
> And finally I've switched the relevent pins to GPIO_FUNC3 in gpio.c.
> Linux sees device 17.0 in lspci and loads the module but doesn't show any
> mmcblk devices.
> I was supplied the board with an Insyde systems EFI firmware which I really
> don't want to use.
> This does recognise the eMMC, boots the same kernel I used with coreboot and
> now I can access the eMMC.
> So I know there is nothing electrically wrong here.
> Should this configuration work with coreboot?
> If I look in the non-fsp baytrail directory I can see emmc.c which appears
> to contain explicit code to initialise the controller.
> There is no equivelent code in the fsp_baytrail directory that I can see.
> Is FSP supposed to initialise the controller or is there something missing
> Thanks for any help
> coreboot mailing list: coreboot at coreboot.org
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