[coreboot] GM45 S3 resume issues

Nico Huber nico.h at gmx.de
Wed Nov 11 22:50:57 CET 2015


On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote:
> I've been looking into S3 resume on GM45 mainboards, which often fails
> in rather interesting ways.
Well, the S3 support wasn't really tested during GM45 development. Maybe
it's just plainly broken. My development system at work (roda/rk9)
doesn't resume because of another problem (but didn't fail raminit on
the resume path in 3 of 3 tries). So it will need some work before I can
test this.

Thanks for taking the time to test on different systems and looking into
this. Can you try to find out which processors (model, stepping) and
northbridge stepping was used? Also did you use the latest processor

> [1]: Tangentially, I noticed that the i82801ix reset_tco_status() says
>      "Don't clear BOOT_STS before SECOND_TO_STS" when it clears
>      BOOT_STS.  In the next two lines it clears BOOT_STS if set.  It
>      never clears SECOND_TO_STS.  Is this a bug?  However, according to
>      the ICH9 datasheet, there is no SECOND_TO_STS bit in TCO1_STS (the
>      high bits of that register are reserved).
Those are R/WC read/write-clear bits. The bits get cleared by writing
a '1'. That's for convenience as you can clear them all by writing the
value you just read. If there is a SECOND_TO_STS bit and it's set, it
gets automagically cleared by the first write (by writing the value we
read before). Clearing BOOT_STS gets deferred to the second write.

Ah, just had a closer look at the datasheet: The bits are defined in the
next register. I'm not sure if it's valid to read/write both registers
at once with a 32-bit access, though. But it seems to work for other
chipsets (e.g. i82801gx, bd82x6x).


More information about the coreboot mailing list