[coreboot] G505s status (and test report)

echelon at free.fr echelon at free.fr
Sun Nov 8 13:08:23 CET 2015

Thank you Felix!
And also I see that your tool fch_xhci_rom_dumper is on github, great!..
As for adding support for Bolton and refactoring and unifying the FCH code, I would like to pick up the task, because I want to invest myself in coreboot dev again and I hope that I will have some time to spend in the near future...
But I need to understand a little bit more the current architecture of coreboot and also the impact of recent developpements like the (proposed) switch from AGESA to native init..
But just to have an idea of the complexity of this task (refactoring amd fch code) can you give me some details of what needs to be done?

----- Mail d'origine -----
De: Felix Held <felix-coreboot at felixheld.de>
À: coreboot at coreboot.org
Envoyé: Sun, 08 Nov 2015 04:57:05 +0100 (CET)
Objet: Re: [coreboot] G505s status (and test report)

Hi Florentin!

>   -3) The USB3 does NOT work : the 3rdparty xhci blob (${COREBOOT}/3rdparty/blobs/southbridge/amd/hudson/xhci.bin) is not correct!..
> PLEASE HELP : can someone give me a tip or advice, how to extract this blob (from uefi image or/sys/<whatever..>)?
You have to use the Bolton USB3 blob if you want to get USB3 somewhere 
near working; it's in the blobs repo. The laptop uses a Bolton and not a 
Hudson FCH, which have a newer version of the XHCI controller component 
(I've verified that they have different boot-ROMs; my 
fch_xhci_rom_dumper can extract both ).
I wrote some patch selecting the right blob (still somewhere in gerrit), 
but you need to patch the vendorcode to get USB3 working (at least at 
some place in the code it matches onto the PCI ID of the XHCI 
controller, which is different). I stopped my efforts to add support for 
Bolton to source AGESA, since doing stuff right would at least imply 
refactoring and unifying the FCH code if not rewriting it and I'm not 
really motivated to do that in my spare time.


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