[coreboot] PCI BAR resource problem

Aaron Durbin adurbin at chromium.org
Fri Mar 7 03:41:48 CET 2014

On Thu, Mar 6, 2014 at 5:06 AM, WANG Siyuan <wangsiyuanbuaa at gmail.com> wrote:
> Hi,
> I have a question about assigning PCI BAR resource.
> In OliveHill, internal graphics(bus 0, dev 1, func 0)'s BAR0 (base address
> register) is 0xe000000c. This is Graphic Memory Base Address.
> I want to change this value to 0xc000000c. I have to do 2 things:
> 1) alloc resource at 0xc0000000 whose length is 512M
> 2) write the address value to internal graphics(bus 0, dev 1, func 0)'s BAR0

Is there a reason why you don't want to auto-assign the resource?

> for 1), maybe I can alloc resource when reading resource.
> but I don't know how to deal with 2). It seems that, BAR's resources are
> assigned by device's ops->set_resources() function. But I can't find this
> function.

There are a few options you can do. Let's use haswell's northbridge
code as an example:

First, you need to have a driver bound to your pci didvid. lines 470
thru 474 bind operations to pci didvid. Within the ops structure
(lines 460-468) has the callbacks associated with the device. There,
you'll find read_resources(), etc.

I think your best bet is to define in your own read_resources(). In
that call pci_dev_read_resources(dev) (line 389, e.g.). Then call
find_resource(dev, PCI_BASE_ADDRESS_X) to obtain the associated
resource for the BAR in question.

res = find_resource(dev, PCI_BASE_ADDRESS_X);
res->flags |= IORESOURCE_FIXED;
res->base = 0xc0000000;

Be sure you that pci_dev_set_resources() and
pci_dev_enable_resources() in the set_resources() and
enable_resources() callbacks, respectively.

I think that should do what you need. I still am of the opinion you
shouldn't be doing this manually. I'm wondering why you think it is

> My question is
> 1) when internal graphics(bus 0, dev 1, func 0)'s BAR0 is set to 0xe0000000?
> How can I change it?
> 2) How does coreboot alloc resources on 0xe0000000? I also can't find it.
> This is a general question: how does coreboot assign PCI device's BAR
> resource?

For all non-fixed resources it will use the available address space
for assigning those. Most of the hard work (at least more pointers
into things to look at) is in pci_device.c:


That is from http://www.chromium.org/chromium-os/2014-firmware-summit
which also has videos.

Hope that helps.


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