[coreboot] Improvement of coreboot code (was: latest baytrail fsp on CRB)

Karl-Heinz Nirschl kh.nirschl at gmail.com
Sat Jun 21 13:45:29 CEST 2014

Hi Paul,

last time was with a yonah / 945gm / ich7 based system. i think that was
3-4 years ago (coreboot v2?)

maybe that statement is somewhat subjective and i have just more experience
with stuff like that in the meantime. i don't have that code anymore but i
think things a
just more straight forward and understandable.

moreover i found it was a lot easier to get a working build that at least
puts out some postcodes and debug log. i think it didn't even compile
without modifications the last time.
an very important reason is that i have excatly the same board - having
(intel) reference boards actively supported makes starting much easier.
last time it was hard to find a supported mainboard that could be bought

best regards,


2014-06-21 10:00 GMT+02:00 Paul Menzel <paulepanter at users.sourceforge.net>:

> Dear Karl-Heinz,
> Am Freitag, den 20.06.2014, 21:17 +0200 schrieb Karl-Heinz Nirschl:
> > i did some experiments with the baytrail fsp coreboot and first of all i
> > like to say thanks for all the good code! everything looks much better
> than
> > the last time i tried to do anything with coreboot.
> could you please elaborate on that statement? When was that last time
> and what device/board did you look at? I ask because in my experience
> the majority of coreboot code lives up to a high standard since several
> years now.
> […]
> Thanks,
> Paul
> --
> coreboot mailing list: coreboot at coreboot.org
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