[coreboot] C720 swapparoo

Duncan Laurie dlaurie at chromium.org
Wed Jan 29 21:54:51 CET 2014

On Wed, Jan 29, 2014 at 11:30 AM, John Lewis <jlewis at johnlewis.ie> wrote:
> Forgot to hit reply to all/list, again ...
> On 29/01/14 19:14, Duncan Laurie wrote:
>> Of course you could also replace the payload with SeaBIOS directly if
>> you are so inclined.  This is just a way to enable default legacy mode
>> without having to modify the underlying firmware.
>> -duncan
> Many thanks for the comprehensive answer, Duncan. That will certainly keep
> many C720 users happy. However, as I would also ultimately like to get rid
> of nag screens, etc, the quoted bit above leads me to more questions. What
> do you mean by replacing the payload, literally replacing one of the
> payloads or compiling my own coreboot? As the binaries are not in the
> third-party repo, is it possible to successfully extract and use them from
> the stock ROM?

Yes you should be able to extract and re-use the binaries from the
existing firmware on the device if you want to rebuild everything.

There are a handful of binaries to worry about with the recent Intel
Chromebook devices.  The first set is located at specific offsets
within the flash:

- The SPI flash descriptor, which lives at the bottom 4K of the SPI
chip in the SI_DESC region of the flashmap.  It is readable from the
host but not writable.
- The Management Engine binary, which lives at the bottom 2MB (-4K for
the descriptor) of the SPI chip in the SI_ME region of the flashmap.
It is neither readable or writable from the host.

Overall this means the bottom 2MB of the 8MB flash (SI_ALL region in
flashmap) should remain constant and from the host point of view it
cannot be modified with SPI transactions.  This can cause issues for
flashrom depending on usage, but it is the same behavior as previous
Sandybridge/Ivybridge generations.

For the basic coreboot+payload (BOOT_STUB region in flashmap) the
binaries are all in CBFS and can be read out with the usual 'cbfstool
bios.bin extract -n NAME -f NAME'

- The mainboard-specific DIMM SPDs, stored as "spd.bin" (also checked
in to the mainboard directory in coreboot)
- The reference code binary, which is stored as "mrc.bin"
- The Video BIOS, which is stored as "pci8086,0406.rom"
- The microcode, which is stored as "cpu_microcode_blob.bin"  (with
recent changes this may be handled differently upstream now)

That should provide all the pieces needed to compile a new coreboot
with the payload of your choice.


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