[coreboot] New patch to review for coreboot: dd68832 AMD S3: Add missing erasing flash sector for MTRR register

Zheng Bao (zheng.bao@amd.com) gerrit at coreboot.org
Thu Feb 7 06:54:32 CET 2013

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2304


commit dd688325831a8a9bc89a7105ab4d8de2a045f7d0
Author: Zheng Bao <fishbaozi at gmail.com>
Date:   Thu Feb 7 13:46:17 2013 +0800

    AMD S3: Add missing erasing flash sector for MTRR register
    Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>
 src/cpu/amd/agesa/s3_resume.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 7069c77..5b4c2c3 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -168,6 +168,8 @@ void OemAgesaSaveMtrr(void)
 	flash->spi->rw = SPI_WRITE_FLAG;
+	flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE);
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr_data = rdmsr(SYS_CFG);
 	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;

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