[coreboot] Reasons for `Boot failed` message?
Paul Menzel
paulepanter at users.sourceforge.net
Sat Apr 6 01:42:33 CEST 2013
Dear coreboot folks,
on the ASRock E350M1 I build coreboot (hash 44af3db) with the VGA ROM
and GRUB as payload.
$ build/cbfstool build/coreboot.rom print
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
offset 0x0
alignment: 64 bytes
Name Offset Type Size
cmos_layout.bin 0x0 cmos_layout 1776
pci1002,9802.rom 0x740 optionrom 65536
fallback/romstage 0x10780 stage 347052
fallback/coreboot_ram 0x65380 stage 205897
fallback/payload 0x97840 payload 195518
(empty) 0xc7440 null 337698
And now it fails and I only updated the coreboot code revision.
[…]
SMBIOS tables: 275 bytes.
Adding CBMEM entry as no. 6
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 57df
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0xc7fee000
rom_table_end = 0xc7fee000
... aligned to 0xc7ff0000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-00000000c7fdffff: RAM
3. 00000000c7fe0000-00000000c7ffffff: CONFIGURATION TABLES
4. 00000000c8000000-00000000dfffffff: RESERVED
5. 00000000f8000000-00000000f8ffffff: RESERVED
6. 0000000100000000-000000021effffff: RAM
Wrote coreboot table at: c7fee000, 0x200 bytes, checksum c1b6
coreboot table: 536 bytes.
Multiboot Information structure has been written.
FREE SPACE 0. c7ff6000 0000a000
GDT 1. c7fe0200 00000200
IRQ TABLE 2. c7fe0400 00001000
SMP TABLE 3. c7fe1400 00001000
ACPI 4. c7fe2400 0000b400
SMBIOS 5. c7fed800 00000800
COREBOOT 6. c7fee000 00008000
CBFS: Looking for 'fallback/payload' starting from 0x0.
CBFS: (unmatched file @0x0: cmos_layout.bin)
CBFS: (unmatched file @0x740: pci1002,9802.rom)
CBFS: (unmatched file @0x10780: fallback/romstage)
CBFS: (unmatched file @0x65380: fallback/coreboot_ram)
CBFS: Found file (offset=0x97878, len=195518).
Loading segment from rom address 0xffc97878
code (compression=1)
New segment dstaddr 0x8200 memsize 0xe504 srcaddr 0xffc978cc filesize 0x417d
(cleaned up) New segment addr 0x8200 size 0xe504 offset 0xffc978cc filesize 0x417d
Loading segment from rom address 0xffc97894
code (compression=1)
New segment dstaddr 0x100000 memsize 0x85b64 srcaddr 0xffc9ba49 filesize 0x2b9ed
(cleaned up) New segment addr 0x100000 size 0x85b64 offset 0xffc9ba49 filesize 0x2b9ed
Loading segment from rom address 0xffc978b0
Entry Point 0x00008200
Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d
lb: [0x0000000000200000, 0x0000000000370038)
Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d
using LZMA
[ 0x00008200, 0000f14f, 0x00016704) <- ffc978cc
Clearing Segment: addr: 0x000000000000f14f memsz: 0x00000000000075b5
dest 00008200, end 00016704, bouncebuffer c7cfff90
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed
lb: [0x0000000000200000, 0x0000000000370038)
Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed
using LZMA
Boot failed
Unfortunately I do not understand what is happening above. Could you
give me a hint, what went wrong, please?
Thanks,
Paul
coreboot-4.0-3980-g44af3db Fri Apr 5 14:04:48 CEST 2013 starting...
BSP Family_Model: 00500f10
cpu_init_detectedx = 00000000
agesawrapper_amdinitmmio passed.
agesawrapper_amdinitreset passed.
agesawrapper_amdinitearly BSP Family_Model: 00500f10
cpu_init_detectedx = 00000001
agesawrapper_amdinitmmio passed.
agesawrapper_amdinitreset passed.
agesawrapper_amdinitearly passed.
agesawrapper_amdinitpost passed.
agesawrapper_amdinitenv passed.
Loading image.
CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
CBFS: (unmatched file @0x0: cmos_layout.bin)
CBFS: (unmatched file @0x740: pci1002,9802.rom)
CBFS: (unmatched file @0x10780: fallback/romstage)
CBFS: Found file (offset=0x653b8, len=205897).
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1507384 bytes), entry @ 0x200000
Jumping to image.
coreboot-4.0-3980-g44af3db Fri Apr 5 14:04:48 CEST 2013 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Mainboard E350M1 Enable.
scan_static_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000002
setup_uma_memory: uma size 0x18000000, memory start 0xc8000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
PCI: 00:01.0 [1002/9802] enabled
PCI: 00:01.1 [1002/1314] enabled
PCI: Static device PCI: 00:04.0 not found, disabling it.
sb800_enable() SB800 - Smbus.c - alink_ab_indx - Start.
SB800 - Smbus.c - alink_ab_indx - End.
PCI: 00:11.0 [1002/4390] enabled
sb800_enable() PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable() PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable() PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable() PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable() sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 24 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
sb800_enable() hda enabled
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb800_enable() PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable() Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:15.0 subordinate bus PCI Express
PCI: 00:15.0 [1002/43a0] enabled
sb800_enable() PCI: 00:16.0 [1002/4397] ops
PCI: 00:16.0 [1002/4397] disabled
sb800_enable() SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
SB800 - Late.c - sb800_callout_entry - Start.
SB800 - Late.c - sb800_callout_entry - End.
PCI: 00:18.0 [1022/1700] enabled
PCI: 00:18.1 [1022/1701] enabled
PCI: 00:18.2 [1022/1702] enabled
PCI: 00:18.3 [1022/1703] enabled
PCI: 00:18.4 [1022/1704] enabled
PCI: 00:18.5 [1022/1718] enabled
PCI: 00:18.6 [1022/1716] enabled
PCI: 00:18.7 [1022/1719] enabled
PCI: Left over static devices:
PCI: 00:15.1
PCI: 00:15.2
PCI: 00:15.3
PCI: Check your devicetree.cb.
scan_static_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
PNP: 002e.b enabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:15.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
PCI: pci_scan_bus returning with max=002
scan_static_bus for Root Device done
done
found VGA at PCI: 00:01.0
Setting up VGA for PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Fam14h - domain_read_resources
DOMAIN: 0000 read_resources bus 0 link: 0
Fam14h - nb_read_resources
PCI: 00:14.0 read_resources bus 0 link: 0
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
PCI: 00:14.0 read_resources bus 0 link: 0 done
SB800 - Lpc.c - lpc_read_resources - Start.
SB800 - Lpc.c - lpc_read_resources - End.
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 1 link: 0
PCI: 00:14.4 read_resources bus 1 link: 0 done
PCI: 00:15.0 register 10(ffffffff), read-only ignoring it
PCI: 00:15.0 register 14(ffffffff), read-only ignoring it
PCI: 00:15.0 register 38(ffffffff), read-only ignoring it
PCI: 00:15.0 read_resources bus 2 link: 0
PCI: 00:15.0 read_resources bus 2 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
PCI: 00:01.1
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 00:50
I2C: 00:50
I2C: 00:51
PCI: 00:14.1
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 002e.6
PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.7
PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.8
PNP: 002e.9
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PCI: 00:14.4
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:15.0
PCI: 00:16.0
PCI: 00:16.2
PCI: 00:18.0
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:18.6
PCI: 00:18.7
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 14 * [0x0 - 0xff] io
PCI: 00:11.0 20 * [0x400 - 0x40f] io
PCI: 00:11.0 10 * [0x410 - 0x417] io
PCI: 00:11.0 18 * [0x418 - 0x41f] io
PCI: 00:11.0 14 * [0x420 - 0x423] io
PCI: 00:11.0 1c * [0x424 - 0x427] io
DOMAIN: 0000 compute_resources_io: base: 428 size: 428 align: 8 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 18 * [0x10000000 - 0x1003ffff] mem
PCI: 00:01.1 10 * [0x10040000 - 0x10043fff] mem
PCI: 00:14.2 10 * [0x10044000 - 0x10047fff] mem
PCI: 00:12.0 10 * [0x10048000 - 0x10048fff] mem
PCI: 00:13.0 10 * [0x10049000 - 0x10049fff] mem
PCI: 00:14.5 10 * [0x1004a000 - 0x1004afff] mem
PCI: 00:11.0 24 * [0x1004b000 - 0x1004b3ff] mem
PCI: 00:12.2 10 * [0x1004b400 - 0x1004b4ff] mem
PCI: 00:13.2 10 * [0x1004b500 - 0x1004b5ff] mem
PCI: 00:14.3 a0 * [0x1004b600 - 0x1004b600] mem
DOMAIN: 0000 compute_resources_mem: base: 1004b601 size: 1004b601 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 00:50
constrain_resources: I2C: 00:51
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 002e.2
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.a
constrain_resources: PNP: 002e.b
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:15.0
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.5
constrain_resources: PCI: 00:18.6
constrain_resources: PCI: 00:18.7
avoid_fixed_resources2: DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit f7ffffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:1000 size:428 align:8 gran:0 limit:ffff
Assigned: PCI: 00:01.0 14 * [0x1000 - 0x10ff] io
Assigned: PCI: 00:11.0 20 * [0x1400 - 0x140f] io
Assigned: PCI: 00:11.0 10 * [0x1410 - 0x1417] io
Assigned: PCI: 00:11.0 18 * [0x1418 - 0x141f] io
Assigned: PCI: 00:11.0 14 * [0x1420 - 0x1423] io
Assigned: PCI: 00:11.0 1c * [0x1424 - 0x1427] io
DOMAIN: 0000 allocate_resources_io: next_base: 1428 size: 428 align: 8 gran: 0 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:1004b601 align:28 gran:0 limit:f7ffffff
Assigned: PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:01.0 18 * [0xf0000000 - 0xf003ffff] mem
Assigned: PCI: 00:01.1 10 * [0xf0040000 - 0xf0043fff] mem
Assigned: PCI: 00:14.2 10 * [0xf0044000 - 0xf0047fff] mem
Assigned: PCI: 00:12.0 10 * [0xf0048000 - 0xf0048fff] mem
Assigned: PCI: 00:13.0 10 * [0xf0049000 - 0xf0049fff] mem
Assigned: PCI: 00:14.5 10 * [0xf004a000 - 0xf004afff] mem
Assigned: PCI: 00:11.0 24 * [0xf004b000 - 0xf004b3ff] mem
Assigned: PCI: 00:12.2 10 * [0xf004b400 - 0xf004b4ff] mem
Assigned: PCI: 00:13.2 10 * [0xf004b500 - 0xf004b5ff] mem
Assigned: PCI: 00:14.3 a0 * [0xf004b600 - 0xf004b600] mem
DOMAIN: 0000 allocate_resources_mem: next_base: f004b601 size: 1004b601 align: 28 gran: 0 done
PCI: 00:14.4 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:14.4 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:14.4 allocate_resources_mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Fam14h - domain_set_resources
amsr - incoming dev = 0027a960
adsr: (before) basek = 0, limitk = 21effffff.
adsr: (after) basek = 0, limitk = 87bfff, sizek = 87c000.
adsr - 0xa0000 to 0xbffff resource.
adsr: mmio_basek=00380000, basek=00000300, limitk=0087bfff
split: 128K table at =c7fe0000
0: mmio_basek=00380000, basek=00400000, limitk=0087bfff
adsr - mmio_basek = 380000.
adsr - high_tables_size = 20000.
DOMAIN: 0000 assign_resources, bus 0 link: 0
Fam14h - nb_set_resources
Fam14h - create_vga_resource
Fam14h - set_resource
PCI: 00:00.0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000 gran 0x00 mem <mmconfig>
PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:01.0 18 <- [0x00f0000000 - 0x00f003ffff] size 0x00040000 gran 0x12 mem
PCI: 00:01.1 10 <- [0x00f0040000 - 0x00f0043fff] size 0x00004000 gran 0x0e mem
PCI: 00:11.0 10 <- [0x0000001410 - 0x0000001417] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000001420 - 0x0000001423] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000001418 - 0x000000141f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000001424 - 0x0000001427] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f004b000 - 0x00f004b3ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f0048000 - 0x00f0048fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00f004b400 - 0x00f004b4ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f0049000 - 0x00f0049fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00f004b500 - 0x00f004b5ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.2 10 <- [0x00f0044000 - 0x00f0047fff] size 0x00004000 gran 0x0e mem64
SB800 - Lpc.c - lpc_set_resources - Start.
PCI: 00:14.3 a0 <- [0x00f004b602 - 0x00f004b602] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io
PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
SB800 - Lpc.c - lpc_set_resources - End.
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:14.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:14.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:14.5 10 <- [0x00f004a000 - 0x00f004afff] size 0x00001000 gran 0x0c mem
DOMAIN: 0000 assign_resources, bus 0 link: 0
adsr - leaving this lovely routine.
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 1000 size 428 align 8 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base e0000000 size 1004b601 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0 flags e0004200 index 20
DOMAIN: 0000 resource base 100000000 size 11efffc00 align 0 gran 0 limit 0 flags e0004200 index 30
DOMAIN: 0000 resource base c8000000 size 18000000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:01.0
PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit f7ffffff flags 60001200 index 10
PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
PCI: 00:01.0 resource base f0000000 size 40000 align 18 gran 18 limit f7ffffff flags 60000200 index 18
PCI: 00:01.1
PCI: 00:01.1 resource base f0040000 size 4000 align 14 gran 14 limit f7ffffff flags 60000200 index 10
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:11.0
PCI: 00:11.0 resource base 1410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
PCI: 00:11.0 resource base 1420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
PCI: 00:11.0 resource base 1418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
PCI: 00:11.0 resource base 1424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
PCI: 00:11.0 resource base 1400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 00:11.0 resource base f004b000 size 400 align 10 gran 10 limit f7ffffff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base f0048000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base f004b400 size 100 align 8 gran 8 limit f7ffffff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base f0049000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base f004b500 size 100 align 8 gran 8 limit f7ffffff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 00:50
I2C: 00:50
I2C: 00:51
PCI: 00:14.1
PCI: 00:14.2
PCI: 00:14.2 resource base f0044000 size 4000 align 14 gran 14 limit f7ffffff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base f004b602 size 1 align 0 gran 0 limit f7ffffff flags 60000200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 002e.6
PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.7
PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.8
PNP: 002e.9
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PCI: 00:14.4
PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 00:14.5
PCI: 00:14.5 resource base f004a000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10
PCI: 00:15.0
PCI: 00:16.0
PCI: 00:16.2
PCI: 00:18.0
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:18.6
PCI: 00:18.7
Done allocating resources.
Enabling resources...
Fam14h - domain_enable_resources
agesawrapper_amdinitmid passed.
ader - leaving domain_enable_resources.
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1510
PCI: 00:01.0 cmd <- 07
PCI: 00:01.1 subsystem <- 1022/1510
PCI: 00:01.1 cmd <- 02
PCI: 00:11.0 subsystem <- 1022/1510
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/1510
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/1510
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/1510
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/1510
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/1510
PCI: 00:14.0 cmd <- 403
PCI: 00:14.2 subsystem <- 1022/1510
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/1510
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 subsystem <- 1022/1510
PCI: 00:14.4 cmd <- 21
PCI: 00:14.5 subsystem <- 1022/1510
PCI: 00:14.5 cmd <- 02
PCI: 00:15.0 bridge ctrl <- ffff
PCI: 00:15.0 cmd <- ffff
PCI: 00:18.0 subsystem <- 1022/1510
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/1510
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/1510
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 subsystem <- 1022/1510
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/1510
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 subsystem <- 1022/1510
PCI: 00:18.5 cmd <- 00
PCI: 00:18.6 subsystem <- 1022/1510
PCI: 00:18.6 cmd <- 00
PCI: 00:18.7 subsystem <- 1022/1510
PCI: 00:18.7 cmd <- 00
W83627HF HWM SMBus enabled
done.
Initializing devices...
Root Device init
CPU_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor AMD device 500f10
CPU: family 14, model 01, stepping 00
Model 14 Init.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Enabling cache
Setting up local apic... apic_id: 0x00 done.
model_14_init done.
CPU #0 initialized
CPU1: stack_base 00290000, stack_end 0029fff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 500f10
CPU: family 14, model 01, stepping 00
Model 14 Init.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Enabling cache
Setting up local apic... apic_id: 0x01 done.
model_14_init done.
CPU #1 initialized
All AP CPUs stopped (2222 loops)
CPU1: stack: 00290000 - 002a0000, lowest used address 0029fda8, stack used: 600 bytes
PCI: 00:00.0 init
Northbridge init
PCI: 00:01.0 init
CBFS: Looking for 'pci1002,9802.rom' starting from 0x0.
CBFS: (unmatched file @0x0: cmos_layout.bin)
CBFS: Found file (offset=0x778, len=65536).
In CBFS, ROM address for PCI: 00:01.0 = ffc00778
PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b4
PCI ROM image, vendor ID 1002, device ID 9802,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from ffc00778 to 0xc0000, 0xe200 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
PCI: 00:01.1 init
PCI: 00:11.0 init
PCI: 00:14.0 init
PCI: 00:14.3 init
SB800 - Late.c - lpc_init - Start.
RTC Init
SB800 - Late.c - lpc_init - End.
PCI: 00:14.4 init
PCI: 00:18.0 init
PCI: 00:18.1 init
PCI: 00:18.2 init
PCI: 00:18.3 init
PCI: 00:18.4 init
PCI: 00:18.5 init
PCI: 00:18.6 init
PCI: 00:18.7 init
PNP: 002e.2 init
PNP: 002e.5 init
PNP: 002e.a init
PNP: 002e.b init
base = 0x0295, reg = 0x40, value = 0x83
base = 0x0295, reg = 0x48, value = 0x2a
base = 0x0295, reg = 0x4a, value = 0x21
base = 0x0295, reg = 0x4e, value = 0x80
base = 0x0295, reg = 0x43, value = 0xff
base = 0x0295, reg = 0x44, value = 0x3f
base = 0x0295, reg = 0x4c, value = 0x18
base = 0x0295, reg = 0x4d, value = 0x95
Devices initialized
Show all devs...After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 0
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
APIC: 01: enabled 1
Re-Initializing CBMEM area to 0xc7fe0000
Initializing CBMEM area to 0xc7fe0000 (131072 bytes)
dword=c7fe0000
nvram_pos=f8, dword>>(8*i)=0
nvram_pos=f9, dword>>(8*i)=0
nvram_pos=fa, dword>>(8*i)=fe
nvram_pos=fb, dword>>(8*i)=c7
Adding CBMEM entry as no. 1
Moving GDT to c7fe0200...ok
High Tables Base is c7fe0000.
agesawrapper_amdinitlate: AmdLateParamsPtr = 2003C
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0xc7fe0400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f0514
Adding CBMEM entry as no. 3
Wrote the mp table end at: c7fe1410 - c7fe1514
MP table: 276 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at c7fe2400...
ACPI: * DSDT at c7fe24c8
ACPI: * DSDT @ c7fe24c8 Length 28e6
ACPI: * FACS at c7fe4db0
ACPI: * FADT at c7fe4df0
ACPI_BLK_BASE: 0x0800
ACPI: added table 1/32, length now 40
ACPI: * HPET at c7fe4ee8
ACPI: added table 2/32, length now 44
ACPI: * MADT at c7fe4f20
ACPI: added table 3/32, length now 48
ACPI: added table 4/32, length now 52
ACPI: * SRAT at c7fe4fa8
AGESA SRAT table NULL. Skipping.
ACPI: * SLIT at c7fe4fa8
AGESA SLIT table NULL. Skipping.
ACPI: * AGESA ALIB SSDT at c7fe4fb0
ACPI: added table 5/32, length now 56
ACPI: * AGESA SSDT Pstate at c7fe6640
ACPI: added table 6/32, length now 60
ACPI: * coreboot TOM SSDT2 at c7fe6a20
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 18021 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: c7fed800
Root Device (ASROCK E350M1)
CPU_CLUSTER: 0 (AMD Family 14h Root Complex)
APIC: 00 (AMD CPU Family 14h)
DOMAIN: 0000 (AMD Family 14h Root Complex)
PCI: 00:00.0 (AMD Family 14h Northbridge)
PCI: 00:01.0 (AMD Family 14h Northbridge)
PCI: 00:01.1 (AMD Family 14h Northbridge)
PCI: 00:04.0 (AMD Family 14h Northbridge)
PCI: 00:05.0 (AMD Family 14h Northbridge)
PCI: 00:06.0 (AMD Family 14h Northbridge)
PCI: 00:07.0 (AMD Family 14h Northbridge)
PCI: 00:08.0 (AMD Family 14h Northbridge)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 00:50 (unknown)
I2C: 00:51 (unknown)
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 002e.0 (Winbond W83627HF Super I/O)
PNP: 002e.1 (Winbond W83627HF Super I/O)
PNP: 002e.2 (Winbond W83627HF Super I/O)
PNP: 002e.3 (Winbond W83627HF Super I/O)
PNP: 002e.5 (Winbond W83627HF Super I/O)
PNP: 002e.6 (Winbond W83627HF Super I/O)
PNP: 002e.7 (Winbond W83627HF Super I/O)
PNP: 002e.8 (Winbond W83627HF Super I/O)
PNP: 002e.9 (Winbond W83627HF Super I/O)
PNP: 002e.a (Winbond W83627HF Super I/O)
PNP: 002e.b (Winbond W83627HF Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:15.1 (ATI SB800)
PCI: 00:15.2 (ATI SB800)
PCI: 00:15.3 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:16.2 (ATI SB800)
PCI: 00:18.0 (AMD Family 14h Northbridge)
PCI: 00:18.1 (AMD Family 14h Northbridge)
PCI: 00:18.2 (AMD Family 14h Northbridge)
PCI: 00:18.3 (AMD Family 14h Northbridge)
PCI: 00:18.4 (AMD Family 14h Northbridge)
PCI: 00:18.5 (AMD Family 14h Northbridge)
PCI: 00:18.6 (AMD Family 14h Northbridge)
PCI: 00:18.7 (AMD Family 14h Northbridge)
APIC: 01 (unknown)
SMBIOS tables: 275 bytes.
Adding CBMEM entry as no. 6
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 57df
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0xc7fee000
rom_table_end = 0xc7fee000
... aligned to 0xc7ff0000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-00000000c7fdffff: RAM
3. 00000000c7fe0000-00000000c7ffffff: CONFIGURATION TABLES
4. 00000000c8000000-00000000dfffffff: RESERVED
5. 00000000f8000000-00000000f8ffffff: RESERVED
6. 0000000100000000-000000021effffff: RAM
Wrote coreboot table at: c7fee000, 0x200 bytes, checksum c1b6
coreboot table: 536 bytes.
Multiboot Information structure has been written.
FREE SPACE 0. c7ff6000 0000a000
GDT 1. c7fe0200 00000200
IRQ TABLE 2. c7fe0400 00001000
SMP TABLE 3. c7fe1400 00001000
ACPI 4. c7fe2400 0000b400
SMBIOS 5. c7fed800 00000800
COREBOOT 6. c7fee000 00008000
CBFS: Looking for 'fallback/payload' starting from 0x0.
CBFS: (unmatched file @0x0: cmos_layout.bin)
CBFS: (unmatched file @0x740: pci1002,9802.rom)
CBFS: (unmatched file @0x10780: fallback/romstage)
CBFS: (unmatched file @0x65380: fallback/coreboot_ram)
CBFS: Found file (offset=0x97878, len=195518).
Loading segment from rom address 0xffc97878
code (compression=1)
New segment dstaddr 0x8200 memsize 0xe504 srcaddr 0xffc978cc filesize 0x417d
(cleaned up) New segment addr 0x8200 size 0xe504 offset 0xffc978cc filesize 0x417d
Loading segment from rom address 0xffc97894
code (compression=1)
New segment dstaddr 0x100000 memsize 0x85b64 srcaddr 0xffc9ba49 filesize 0x2b9ed
(cleaned up) New segment addr 0x100000 size 0x85b64 offset 0xffc9ba49 filesize 0x2b9ed
Loading segment from rom address 0xffc978b0
Entry Point 0x00008200
Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d
lb: [0x0000000000200000, 0x0000000000370038)
Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d
using LZMA
[ 0x00008200, 0000f14f, 0x00016704) <- ffc978cc
Clearing Segment: addr: 0x000000000000f14f memsz: 0x00000000000075b5
dest 00008200, end 00016704, bouncebuffer c7cfff90
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed
lb: [0x0000000000200000, 0x0000000000370038)
Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed
using LZMA
Boot failed
-------------- next part --------------
#
# Automatically generated make config: don't edit
# coreboot version: 4.0-3980-g44af3db
# Fri Apr 5 14:02:51 2013
#
#
# General setup
#
# CONFIG_EXPERT is not set
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
# CONFIG_ALT_CBFS_LOAD_PAYLOAD is not set
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_SCANBUILD_ENABLE is not set
# CONFIG_CCACHE is not set
# CONFIG_USE_OPTION_TABLE is not set
CONFIG_COMPRESS_RAMSTAGE=y
# CONFIG_INCLUDE_CONFIG_FILE is not set
# CONFIG_EARLY_CBMEM_INIT is not set
# CONFIG_DYNAMIC_CBMEM is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
#
# Mainboard
#
# CONFIG_VENDOR_AAEON is not set
# CONFIG_VENDOR_ABIT is not set
# CONFIG_VENDOR_ADVANSUS is not set
# CONFIG_VENDOR_ADVANTECH is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_ARIMA is not set
# CONFIG_VENDOR_ARTECGROUP is not set
# CONFIG_VENDOR_ASI is not set
CONFIG_VENDOR_ASROCK=y
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_A_TREND is not set
# CONFIG_VENDOR_AVALUE is not set
# CONFIG_VENDOR_AXUS is not set
# CONFIG_VENDOR_AZZA is not set
# CONFIG_VENDOR_BACHMANN is not set
# CONFIG_VENDOR_BCOM is not set
# CONFIG_VENDOR_BIFFEROS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BROADCOM is not set
# CONFIG_VENDOR_COMPAQ is not set
# CONFIG_VENDOR_DIGITALLOGIC is not set
# CONFIG_VENDOR_EAGLELION is not set
# CONFIG_VENDOR_ECS is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_IEI is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_IWAVE is not set
# CONFIG_VENDOR_IWILL is not set
# CONFIG_VENDOR_JETWAY is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LANNER is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIPPERT is not set
# CONFIG_VENDOR_MITAC is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NEC is not set
# CONFIG_VENDOR_NEWISYS is not set
# CONFIG_VENDOR_NOKIA is not set
# CONFIG_VENDOR_NVIDIA is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_RCA is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SOYO is not set
# CONFIG_VENDOR_SUNW is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_TECHNEXION is not set
# CONFIG_VENDOR_TECHNOLOGIC is not set
# CONFIG_VENDOR_TELEVIDEO is not set
# CONFIG_VENDOR_THOMSON is not set
# CONFIG_VENDOR_TRAVERSE is not set
# CONFIG_VENDOR_TYAN is not set
# CONFIG_VENDOR_VIA is not set
# CONFIG_VENDOR_WINENT is not set
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="asrock/e350m1"
CONFIG_MAINBOARD_PART_NUMBER="E350M1"
CONFIG_IRQ_SLOT_COUNT=11
CONFIG_MAINBOARD_VENDOR="ASROCK"
CONFIG_APIC_ID_OFFSET=0x0
CONFIG_HW_MEM_HOLE_SIZEK=0x200000
CONFIG_MAX_CPUS=2
CONFIG_MAX_PHYSICAL_CPUS=1
# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set
CONFIG_MEM_TRAIN_SEQ=2
CONFIG_RAMTOP=0x1000000
CONFIG_HEAP_SIZE=0xc0000
CONFIG_RAMBASE=0x200000
CONFIG_VGA_BIOS_ID="1002,9802"
# CONFIG_BOARD_AMD_DB800 is not set
# CONFIG_BOARD_AMD_DBM690T is not set
# CONFIG_BOARD_AMD_DINAR is not set
# CONFIG_BOARD_AMD_MAHOGANY is not set
# CONFIG_BOARD_AMD_MAHOGANY_FAM10 is not set
# CONFIG_BOARD_AMD_NORWICH is not set
# CONFIG_BOARD_AMD_PISTACHIO is not set
# CONFIG_BOARD_AMD_RUMBA is not set
# CONFIG_BOARD_AMD_SERENGETI_CHEETAH is not set
# CONFIG_BOARD_AMD_SERENGETI_CHEETAH_FAM10 is not set
# CONFIG_BOARD_AMD_TILAPIA_FAM10 is not set
# CONFIG_BOARD_AMD_BIMINI_FAM10 is not set
# CONFIG_BOARD_AMD_INAGUA is not set
# CONFIG_BOARD_AMD_PERSIMMON is not set
# CONFIG_BOARD_AMD_SOUTHSTATION is not set
# CONFIG_BOARD_AMD_TORPEDO is not set
# CONFIG_BOARD_AMD_UNIONSTATION is not set
# CONFIG_BOARD_AMD_PARMER is not set
# CONFIG_BOARD_AMD_THATCHER is not set
CONFIG_STACK_SIZE=0x10000
CONFIG_SIO_PORT=0x2e
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_VGA_BIOS=y
# CONFIG_CONSOLE_POST is not set
# CONFIG_PCI_ROM_RUN is not set
# CONFIG_UDELAY_IO is not set
CONFIG_SERIAL_CPU_INIT=y
CONFIG_ACPI_SSDTX_NUM=0
# CONFIG_SB800_AHCI_ROM is not set
CONFIG_VGA_BIOS_FILE="pci1002,9802.rom"
# CONFIG_BOARD_ASROCK_939A785GMH is not set
CONFIG_BOARD_ASROCK_E350M1=y
# CONFIG_PCI_64BIT_PREF_MEM is not set
CONFIG_MMCONF_BASE_ADDRESS=0xf8000000
CONFIG_XIP_ROM_SIZE=0x100000
# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
CONFIG_LOGICAL_CPUS=y
CONFIG_IOAPIC=y
CONFIG_SMP=y
CONFIG_TTYS0_BAUD=115200
CONFIG_TTYS0_BASE=0x3f8
CONFIG_TTYS0_LCS=3
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
CONFIG_CONSOLE_SERIAL8250=y
# CONFIG_USBDEBUG is not set
# CONFIG_K8_REV_F_SUPPORT is not set
CONFIG_CPU_ADDR_BITS=36
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
CONFIG_COREBOOT_ROMSIZE_KB=4096
CONFIG_ROM_SIZE=0x400000
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_ARCH_X86=y
# CONFIG_ARCH_ARMV7 is not set
#
# Architecture (x86)
#
# CONFIG_AP_IN_SIPI_WAIT is not set
# CONFIG_SIPI_VECTOR_IN_ROM is not set
CONFIG_MAX_REBOOT_CNT=3
CONFIG_X86_BOOTBLOCK_SIMPLE=y
# CONFIG_X86_BOOTBLOCK_NORMAL is not set
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_ROMCC is not set
CONFIG_PC80_SYSTEM=y
# CONFIG_HAVE_CMOS_DEFAULT is not set
CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/cimx/sb800/bootblock.c"
CONFIG_HAVE_ARCH_MEMSET=y
CONFIG_HAVE_ARCH_MEMCPY=y
# CONFIG_BIG_ENDIAN is not set
CONFIG_LITTLE_ENDIAN=y
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
# CONFIG_PCI_CONF2 is not set
CONFIG_HPET_ADDRESS=0xfed00000
CONFIG_ID_SECTION_OFFSET=0x80
#
# Chipset
#
#
# CPU
#
CONFIG_CPU_SOCKET_TYPE=0x10
# CONFIG_EXT_RT_TBL_SUPPORT is not set
# CONFIG_EXT_CONF_SUPPORT is not set
CONFIG_CBB=0x0
CONFIG_CDB=0x18
CONFIG_DIMM_SUPPORT=0x0104
CONFIG_LIFT_BSP_APIC_ID=y
CONFIG_UDELAY_LAPIC_FIXED_FSB=200
CONFIG_CPU_AMD_AGESA=y
CONFIG_HAVE_INIT_TIMER=y
CONFIG_CPU_AMD_AGESA_FAMILY14=y
CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x71000
CONFIG_SMM_TSEG_SIZE=0
# CONFIG_SSE2 is not set
# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
CONFIG_UDELAY_LAPIC=y
# CONFIG_UDELAY_TSC is not set
# CONFIG_UDELAY_TIMER2 is not set
# CONFIG_TSC_CALIBRATE_WITH_IO is not set
CONFIG_TSC_SYNC_LFENCE=y
# CONFIG_TSC_SYNC_MFENCE is not set
# CONFIG_CACHE_ROM is not set
# CONFIG_SMM_TSEG is not set
CONFIG_X86_AMD_FIXED_MTRRS=y
CONFIG_CACHE_AS_RAM=y
CONFIG_AP_SIPI_VECTOR=0xfffff000
# CONFIG_CPU_MICROCODE_IN_CBFS is not set
# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
CONFIG_CPU_MICROCODE_CBFS_NONE=y
#
# Northbridge
#
CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y
CONFIG_VIDEO_MB=0
CONFIG_AMDMCT=y
CONFIG_MMCONF_BUS_NUMBER=16
CONFIG_NORTHBRIDGE_AMD_AGESA=y
# CONFIG_CONSOLE_VGA_MULTI is not set
# CONFIG_S3_VGA_ROM_RUN is not set
CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14=y
# CONFIG_AMD_NB_CIMX is not set
# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
CONFIG_CBFS_SIZE=0x400000
#
# Southbridge
#
CONFIG_AMD_SB_CIMX=y
CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800=y
# CONFIG_ENABLE_IDE_COMBINED_MODE is not set
CONFIG_IDE_COMBINED_MODE=0x1
# CONFIG_SB800_SATA_IDE is not set
CONFIG_SB800_SATA_AHCI=y
# CONFIG_SB800_SATA_RAID is not set
CONFIG_SB800_SATA_MODE=0x2
CONFIG_SB_SUPERIO_HWM=y
CONFIG_AHCI_ROM_ID="1002,4391"
# CONFIG_SB800_IMC_FWM is not set
CONFIG_SB800_NO_FAN_CONTROL=y
# CONFIG_SB800_MANUAL_FAN_CONTROL is not set
# CONFIG_SB800_IMC_FAN_CONTROL is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
# CONFIG_SPI_FLASH is not set
#
# Super I/O
#
CONFIG_SUPERIO_WINBOND_W83627HF=y
#
# Embedded Controllers
#
#
# Devices
#
# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
CONFIG_VGA_ROM_RUN=y
# CONFIG_ON_DEVICE_ROM_RUN is not set
CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
CONFIG_PCI=y
# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_AGP_PLUGIN_SUPPORT=y
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCI_BUS_SEGN_BITS=0
#
# VGA BIOS
#
#
# Display
#
# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set
# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set
#
# PXE ROM
#
# CONFIG_PXE_ROM is not set
#
# Generic Drivers
#
# CONFIG_IPMI_KCS is not set
# CONFIG_DRIVER_MAXIM_MAX77686 is not set
# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
# CONFIG_TPM is not set
# CONFIG_RTL8168_ROM_DISABLE is not set
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_MMCONF_SUPPORT=y
#
# Console
#
CONFIG_DEFAULT_EARLY_CONSOLE=y
CONFIG_EARLY_CONSOLE=y
CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_COM1=y
# CONFIG_CONSOLE_SERIAL_COM2 is not set
# CONFIG_CONSOLE_SERIAL_COM3 is not set
# CONFIG_CONSOLE_SERIAL_COM4 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
# CONFIG_HAVE_USBDEBUG is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
# CONFIG_CONSOLE_LOGBUF is not set
# CONFIG_NO_POST is not set
# CONFIG_CMOS_POST is not set
CONFIG_IO_POST=y
CONFIG_IO_POST_PORT=0x80
CONFIG_HAVE_UART_IO_MAPPED=y
# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
# CONFIG_HAVE_UART_SPECIAL is not set
# CONFIG_HAVE_ACPI_RESUME is not set
# CONFIG_HAVE_ACPI_SLIC is not set
CONFIG_HAVE_HARD_RESET=y
CONFIG_HAVE_OPTION_TABLE=y
# CONFIG_PIRQ_ROUTE is not set
# CONFIG_HAVE_SMI_HANDLER is not set
CONFIG_PCI_IO_CFG_EXT=y
CONFIG_CACHE_ROM_SIZE=0x400000
# CONFIG_USE_WATCHDOG_ON_BOOT is not set
# CONFIG_VGA is not set
CONFIG_GFXUMA=y
# CONFIG_RELOCATABLE_MODULES is not set
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_HAVE_MP_TABLE=y
CONFIG_HAVE_PIRQ_TABLE=y
CONFIG_MAX_PIRQ_LINKS=4
#
# System tables
#
CONFIG_MULTIBOOT=y
CONFIG_GENERATE_ACPI_TABLES=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
#
# Payload
#
# CONFIG_PAYLOAD_NONE is not set
CONFIG_PAYLOAD_ELF=y
# CONFIG_PAYLOAD_SEABIOS is not set
# CONFIG_PAYLOAD_FILO is not set
# CONFIG_PAYLOAD_TIANOCORE is not set
CONFIG_PAYLOAD_FILE="grub2.elf"
CONFIG_COMPRESSED_PAYLOAD_LZMA=y
# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
#
# Debugging
#
# CONFIG_GDB_STUB is not set
# CONFIG_DEBUG_CBFS is not set
# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
# CONFIG_HAVE_DEBUG_CAR is not set
# CONFIG_DEBUG_PIRQ is not set
# CONFIG_HAVE_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_ACPI is not set
# CONFIG_REALMODE_DEBUG is not set
# CONFIG_LLSHELL is not set
# CONFIG_TRACE is not set
# CONFIG_AP_CODE_IN_CAR is not set
# CONFIG_RAMINIT_SYSINFO is not set
# CONFIG_ENABLE_APIC_EXT_ID is not set
# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
# CONFIG_CHROMEOS is not set
-------------- next part --------------
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