[coreboot] New patch to review for coreboot: db21106 rtc: force mc146818 register D to a correct value

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1695

-gerrit

commit db211067bfe2f58578c4cd314f3b8dd956fde173
Author: Vincent Palatin <vpalatin at chromium.org>
Date:   Tue Aug 7 16:05:14 2012 -0700

    rtc: force mc146818 register D to a correct value
    
    On Panther Point PCH (and maybe cougar point), when some of the register
    D reserved bits are set, the RTC starts misbehaving (e.g. incrementing
    the year byte every second).
    There are probably undocumented features implemented behind those bits.
    Let's reset register D to a known state to ensure we get the expected
    RTC behavior.
    
    Change-Id: I7e2c2a2c6130a974bccb3d760b41eaa579a58b67
    Signed-off-by: Vincent Palatin <vpalatin at chromium.org>
---
 src/drivers/pc80/mc146818rtc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index cc14a41..efeb378 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -171,6 +171,8 @@ void rtc_init(int invalid)
 	cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL);
 	/* Setup the frequency it operates at */
 	cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
+	/* Ensure all reserved bits are 0 in register D */
+	cmos_write(RTC_VRT, RTC_VALID);
 
 #if CONFIG_USE_OPTION_TABLE
 	/* See if there is a LB CMOS checksum error */