[coreboot] How to port core boot

[ali hagigat]

I changed romstage .c as follows:

void main(unsigned long bist)
{
	/* Set southbridge and Super I/O GPIOs. */
	mb_gpio_init();

	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();

	report_bist_failure(bist);
	//enable_smbus();
	//dump_spd_registers();
	//sdram_set_registers();
	//sdram_set_spd_registers();
	sdram_enable();
	ram_check(0x00100000, 0x00900000);
}

This time i do ram_check between 1M to 3M, here is the serial port output:

coreboot-4.0-1959-g950f20a-dirty Tue Feb  7 18:39:18 IRST 2012 starting...
Testing DRAM : 00100000 - 00900000
DRAM fill: 0x00100000-0x00900000
00900000
DRAM filled
DRAM verify: 0x00100000-0x00900000
00900000
DRAM range verified.
Done.
Loading image.
Searching for fallback/coreboot_ram
Check fallback/romstage
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.

I only changed sdram_enable() and some commented function calls and
there is no payload.  How these changes can effect Coreboot?

My guess is that the problem occurs inside this function:
cbfs_and_run_core

It is located in:
~/bios/coreboot/src/arch/x86/lib/cbfs_and_run.c

When it wants to do a jump inside cbfs_and_run_core(), the processor
halts some how.

Regards

On Tue, Feb 7, 2012 at 6:27 PM, Kyösti Mälkki <kyosti.malkki at gmail.com> wrote:
> On Tue, 2012-02-07 at 18:08 +0330, ali hagigat wrote:
>> Thank you, Kyösti, for the reply. I tested the modified Coreboot by
>> 115200 Buad rate, again the same message(latest post code seems to be
>> 0x11)(modified Coreboot contains sdram_enable() changed and some
>> fuction calls was commented out in romstage.c  and i am using
>> build/coreboot.rom as the final image on ROM chip):
>>
>> coreboot-4.0-1959-g950f20a-dirty Tue Feb  7 17:40:50 IRST 2012 starting...
>> Testing DRAM : 02000000 - 10000000
>> DRAM fill: 0x02000000-0x10000000
>> 10000000
>> DRAM filled
>> DRAM verify: 0x02000000-0x10000000
>> 10000000
>> DRAM range verified.
>> Done.
>> Loading image.
>> Searching for fallback/coreboot_ram
>> Check fallback/romstage
>> Check fallback/coreboot_ram
>> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
>> lzma: Decoding error = 1
>> FATAL: Essential component is missing.
>
> Your ram_check() still does not cover 1M-3M range. Failure to decompress
> coreboot_ram (lzma decoding error) screams a problem with initialising
> RAM.
>
> KM
>