[coreboot] tyan s2882-d not booting
Kui Zhang
kuizhang at gmail.com
Thu Dec 6 01:14:32 CET 2012
Thanks Guys.
I tried building coreboot under following env:
Ubuntu Qutantal 64bit/32bit. (Both 64bit kernel)
Ubuntu Raring 64bit
Debian Squeeze 64bit.
With both native build-essential and crossgcc.
...
/usr/src/bios/git/coreboot# cat .xcompile
# x86 TARCH_SEARCH=
/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf- i386-elf-
/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/x86_64-elf- x86_64-elf-
# elf32-i386 toolchain
(/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-gcc)
CC_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-gcc
-Wno-unused-but-set-variable -Wa,--divide -fno-stack-protector
-Wl,--build-id=none
AS_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-as
LD_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld
NM_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-nm
OBJCOPY_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-objcopy
OBJDUMP_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-objdump
READELF_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-readelf
STRIP_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-strip
AR_i386:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/i386-elf-ar
# arm TARCH_SEARCH=
/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/littlearm-elf-
littlearm-elf-
IASL:=/usr/src/bios/git/coreboot/util/crossgcc/xgcc/bin/iasl
# native toolchain
HOSTCC:=gcc
...
Results:
Current head boots only with single CPU. Dual cpu with less ram does not
work. And during the initial boot process, on board speaker beeps. It sound
like cpu error with AMI bios. Beep stopped around the same time as loading
CBFS payload (seabios)...
Keyboard stop responding, both usb and ps2, at the the end of boot process.
I did try building older version specified in the wiki. I get this error,
in all built environment.
/usr/bin/ld: section .eh_frame loaded at
[00000000fffbfff0,00000000fffc0667] overlaps section .reset loaded at
[00000000fffbfff0,00000000fffbffff]
commit e89d8a57accbac5066f80266d1e98e63f62ba4c5 sounds like my problem... I
tried to build commits around 1f7d3c5672ec90f8d71907b1a07c8a87fa461047,
none worked with dual cpu...
The problem seem to be, beyond my current skill level :(
Thanks again for the inputs.
Kui.Z
On Tue, Dec 4, 2012 at 7:34 PM, Ward Vandewege <ward at gnu.org> wrote:
> On Mon, Dec 03, 2012 at 05:12:03PM -0800, Kui Zhang wrote:
> > I got some old boxes: tyan s2882-d, dual opteron processors, 16G RAM.
> 512K
> > bios flash.
> >
> > So far, I am not able to get it to boot. It appears to reboot during CPU
> > init.
> >
> > If anyone got coreboot working on this board, which revision did it
> worked
> > last ?
>
> That would have been me, I think. I'm not 100% sure we still have an s2882;
> we only had one if I recall correctly. I can check later this week. Some
> revision(s) it worked with are listed on
> http://www.coreboot.org/Tyan_S2882.
> Those are revisions from the old SVN tree; you can grep the git log for the
> svn revision number (it is listed); you'll see these are revisions from
> 2006.
>
> I do have an s2881 that I booted succesfully about 5 or 6 weeks ago, with
> coreboot head. It's a very similar board.
>
> Have you tried with less ram?
>
> Thanks,
> Ward.
>
> --
> Ward Vandewege | CTO, Free Software Foundation
> GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS
>
> Do you use free software? Donate to join the FSF and support freedom at
> http://www.fsf.org/register_form?referrer=859
>
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coreboot-4.0-3132-g0f5caa2 Wed Dec 5 21:17:46 UTC 2012 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
01 nodes initialized.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
Ram2.00
Enabling dual channel memory
Registered
200MHz
Interleaved
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram2.01
Ram3
ECC enabled
Initializing memory: done
Ram4
v_esp=000cff48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (282624 bytes), entry @ 0x100000
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-3132-g0f5caa2 Wed Dec 5 21:17:46 UTC 2012 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:06.1: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:09.1: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:00.2: enabled 0
PCI: 00:01.0: enabled 0
PCI: 00:05.0: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:08.0: enabled 1
PCI: 00:01.0: enabled 1
PNP: 002e.0: enabled 1
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.2: enabled 1
PCI: 00:01.3: enabled 1
PCI: 00:01.5: enabled 0
PCI: 00:01.6: enabled 0
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
Compare with tree...
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:06.1: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:09.1: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:00.2: enabled 0
PCI: 00:01.0: enabled 0
PCI: 00:05.0: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:08.0: enabled 1
PCI: 00:01.0: enabled 1
PNP: 002e.0: enabled 1
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.2: enabled 1
PCI: 00:01.3: enabled 1
PCI: 00:01.5: enabled 0
PCI: 00:01.6: enabled 0
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
scan_static_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xfc000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
POST: 0x25
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
flags: 0x8000
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
Capability: type 0x08 @ 0xc0
flags: 0x0041
Collapsing PCI: 01:01.0 [1022/7450]
Capability: type 0x08 @ 0xc0
flags: 0x0083
Collapsing PCI: 01:03.0 [1022/7460]
PCI: 01:00.0 [1022/7450] bus ops
PCI: 01:00.0 [1022/7450] enabled
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
flags: 0x8000
Capability: type 0x07 @ 0xa0
Capability: type 0x08 @ 0xb8
Capability: type 0x08 @ 0xc0
flags: 0x0040
PCI: 01:01.0 count: 0002 static_count: 0002
PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003
PCI: 01:00.0 [1022/7460] bus ops
PCI: 01:00.0 [1022/7460] enabled
Capability: type 0x08 @ 0xc0
flags: 0x0080
PCI: 01:03.0 count: 0004 static_count: 0002
PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:01.0 [1022/7450] enabled
PCI: 01:01.1 [1022/7451] ops
PCI: 01:01.1 [1022/7451] enabled
PCI: 01:02.0 [1022/7450] bus ops
PCI: 01:02.0 [1022/7450] enabled
PCI: 01:02.1 [1022/7451] ops
PCI: 01:02.1 [1022/7451] enabled
PCI: 01:03.0 [1022/7460] enabled
PCI: 01:04.0 [1022/7468] bus ops
PCI: 01:04.0 [1022/7468] enabled
PCI: 01:04.1 [1022/7469] ops
PCI: 01:04.1 [1022/7469] enabled
PCI: 01:04.2 [1022/746a] bus ops
PCI: 01:04.2 [1022/746a] enabled
PCI: 01:04.3 [1022/746b] bus ops
PCI: 01:04.3 [1022/746b] enabled
PCI: 01:04.4, bad id 0x0
PCI: 01:04.7, bad id 0x0
POST: 0x25
do_pci_scan_bridge for PCI: 01:01.0
PCI: pci_scan_bus for bus 02
POST: 0x24
PCI: Static device PCI: 02:06.0 not found, disabling it.
PCI: Static device PCI: 02:06.1 not found, disabling it.
PCI: 02:09.0 [14e4/1648] enabled
PCI: 02:09.1 [14e4/1648] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=002
POST: 0x55
Capability: type 0x07 @ 0xa0
PCI: 02: 100MHz PCI-X
Capability: type 0xff @ 0xfc
Capability: type 0xff @ 0xfc
PCI: 01:01.0,0 disabling relaxed ordering
PCI: 00:18.0,0 disabling relaxed ordering
PCI_DOMAIN: 0000,0 disabling relaxed ordering
Root Device,0 disabling relaxed ordering
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 01:02.0
PCI: pci_scan_bus for bus 03
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=003
POST: 0x55
Capability: type 0x07 @ 0xa0
PCI: 03: 133MHz PCI-X
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 01:03.0
PCI: pci_scan_bus for bus 04
POST: 0x24
PCI: 04:00.0 [1022/7464] bus ops
PCI: 04:00.0 [1022/7464] enabled
PCI: 04:00.1 [1022/7464] bus ops
PCI: 04:00.1 [1022/7464] enabled
PCI: 04:05.0 [1095/3114] ops
PCI: 04:05.0 [1095/3114] enabled
PCI: 04:06.0 [1002/4752] enabled
PCI: 04:08.0 [8086/1229] enabled
POST: 0x25
scan_static_bus for PCI: 04:00.0
scan_static_bus for PCI: 04:00.0 done
scan_static_bus for PCI: 04:00.1
scan_static_bus for PCI: 04:00.1 done
PCI: pci_scan_bus returning with max=004
POST: 0x55
do_pci_scan_bridge returns max 4
scan_static_bus for PCI: 01:04.0
PNP: 002e.0 enabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
scan_static_bus for PCI: 01:04.0 done
scan_static_bus for PCI: 01:04.2
scan_static_bus for PCI: 01:04.2 done
scan_static_bus for PCI: 01:04.3
scan_static_bus for PCI: 01:04.3 done
PCI: pci_scan_bus returning with max=004
POST: 0x55
PCI: pci_scan_bus returning with max=004
POST: 0x55
PCI_DOMAIN: 0000 passpw: disabled
scan_static_bus for Root Device done
done
POST: 0x66
found VGA at PCI: 04:06.0
Setting up VGA for PCI: 04:06.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 01:03.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 read_resources bus 1 link: 0
PCI: 01:01.0 read_resources bus 2 link: 0
PCI: 01:01.0 read_resources bus 2 link: 0 done
PCI: 01:03.0 read_resources bus 4 link: 0
PCI: 01:03.0 read_resources bus 4 link: 0 done
PCI: 01:04.0 read_resources bus 0 link: 0
PCI: 01:04.0 read_resources bus 0 link: 0 done
PCI: 01:04.3 read_resources bus 0 link: 0
PCI: 01:04.3 read_resources bus 0 link: 0 done
PCI: 01:04.3 read_resources bus 0 link: 1
PCI: 01:04.3 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 1 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:18.0 child on link 0 PCI: 01:01.0
PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8
PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4
PCI: 01:01.0 child on link 0 PCI: 02:06.0
PCI: 01:01.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 01:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 01:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 02:06.0
PCI: 02:06.1
PCI: 02:09.0
PCI: 02:09.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
PCI: 02:09.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 18
PCI: 02:09.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 02:09.1
PCI: 02:09.1 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
PCI: 02:09.1 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 18
PCI: 02:09.1 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 01:01.1
PCI: 01:01.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
PCI: 01:02.0
PCI: 01:02.1
PCI: 01:02.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
PCI: 01:03.0 child on link 0 PCI: 04:00.0
PCI: 01:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 01:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 01:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 04:00.1
PCI: 04:00.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 04:00.2
PCI: 04:01.0
PCI: 04:05.0
PCI: 04:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 04:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 04:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 04:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 04:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 04:05.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
PCI: 04:05.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
PCI: 04:06.0
PCI: 04:06.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
PCI: 04:06.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 04:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
PCI: 04:06.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 04:08.0
PCI: 04:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 04:08.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14
PCI: 04:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 18
PCI: 01:04.0 child on link 0 PNP: 002e.0
PCI: 01:04.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 01:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 01:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 002e.6
PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.7
PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.8
PNP: 002e.9
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PCI: 01:04.1
PCI: 01:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 01:04.2
PCI: 01:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10
PCI: 01:04.3
PCI: 01:04.3 resource base 0 size 100 align 8 gran 8 limit 10000 flags 100 index 58
PCI: 01:04.5
PCI: 01:04.6
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 01:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 01:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 04:06.0 14 * [0x0 - 0xff] io
PCI: 04:08.0 14 * [0x400 - 0x43f] io
PCI: 04:05.0 20 * [0x440 - 0x44f] io
PCI: 04:05.0 10 * [0x450 - 0x457] io
PCI: 04:05.0 18 * [0x458 - 0x45f] io
PCI: 04:05.0 14 * [0x460 - 0x463] io
PCI: 04:05.0 1c * [0x464 - 0x467] io
PCI: 01:03.0 compute_resources_io: base: 468 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 01:03.0 1c * [0x0 - 0xfff] io
PCI: 01:04.3 58 * [0x1000 - 0x10ff] io
PCI: 01:04.2 10 * [0x1400 - 0x141f] io
PCI: 01:04.1 20 * [0x1420 - 0x142f] io
PCI: 00:18.0 compute_resources_io: base: 1430 size: 2000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 00 * [0x0 - 0x1fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 01:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 01:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:09.0 10 * [0x0 - 0xffff] mem
PCI: 02:09.0 18 * [0x10000 - 0x1ffff] mem
PCI: 02:09.0 30 * [0x20000 - 0x2ffff] mem
PCI: 02:09.1 10 * [0x30000 - 0x3ffff] mem
PCI: 02:09.1 18 * [0x40000 - 0x4ffff] mem
PCI: 02:09.1 30 * [0x50000 - 0x5ffff] mem
PCI: 01:01.0 compute_resources_mem: base: 60000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 01:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:06.0 10 * [0x0 - 0xffffff] mem
PCI: 04:05.0 30 * [0x1000000 - 0x107ffff] mem
PCI: 04:06.0 30 * [0x1080000 - 0x109ffff] mem
PCI: 04:08.0 18 * [0x10a0000 - 0x10bffff] mem
PCI: 04:00.0 10 * [0x10c0000 - 0x10c0fff] mem
PCI: 04:00.1 10 * [0x10c1000 - 0x10c1fff] mem
PCI: 04:06.0 18 * [0x10c2000 - 0x10c2fff] mem
PCI: 04:08.0 10 * [0x10c3000 - 0x10c3fff] mem
PCI: 04:05.0 24 * [0x10c4000 - 0x10c43ff] mem
PCI: 01:03.0 compute_resources_mem: base: 10c4400 size: 1100000 align: 24 gran: 20 limit: ffffffff done
PCI: 01:03.0 20 * [0x0 - 0x10fffff] mem
PCI: 01:01.0 20 * [0x1100000 - 0x11fffff] mem
PCI: 01:01.1 10 * [0x1200000 - 0x1200fff] mem
PCI: 01:02.1 10 * [0x1201000 - 0x1201fff] mem
PCI: 00:18.0 compute_resources_mem: base: 1202000 size: 1300000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem
PCI: 00:18.0 01 * [0x4000000 - 0x52fffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 5300000 size: 5300000 align: 26 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 01:01.0
constrain_resources: PCI: 02:09.0
constrain_resources: PCI: 02:09.1
constrain_resources: PCI: 01:01.1
constrain_resources: PCI: 01:02.1
constrain_resources: PCI: 01:03.0
constrain_resources: PCI: 04:00.0
constrain_resources: PCI: 04:00.1
constrain_resources: PCI: 04:05.0
constrain_resources: PCI: 04:06.0
constrain_resources: PCI: 04:08.0
constrain_resources: PCI: 01:04.0
constrain_resources: PNP: 002e.0
constrain_resources: PNP: 002e.2
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.b
constrain_resources: PCI: 01:04.1
constrain_resources: PCI: 01:04.2
constrain_resources: PCI: 01:04.3
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 000c0000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:03.0 1c * [0x1000 - 0x1fff] io
Assigned: PCI: 01:04.3 58 * [0x2000 - 0x20ff] io
Assigned: PCI: 01:04.2 10 * [0x2400 - 0x241f] io
Assigned: PCI: 01:04.1 20 * [0x2420 - 0x242f] io
PCI: 00:18.0 allocate_resources_io: next_base: 2430 size: 2000 align: 12 gran: 12 done
PCI: 01:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 01:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 01:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 04:06.0 14 * [0x1000 - 0x10ff] io
Assigned: PCI: 04:08.0 14 * [0x1400 - 0x143f] io
Assigned: PCI: 04:05.0 20 * [0x1440 - 0x144f] io
Assigned: PCI: 04:05.0 10 * [0x1450 - 0x1457] io
Assigned: PCI: 04:05.0 18 * [0x1458 - 0x145f] io
Assigned: PCI: 04:05.0 14 * [0x1460 - 0x1463] io
Assigned: PCI: 04:05.0 1c * [0x1464 - 0x1467] io
PCI: 01:03.0 allocate_resources_io: next_base: 1468 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:5300000 align:26 gran:0 limit:febfffff
Assigned: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem
Assigned: PCI: 00:18.0 01 * [0xfc000000 - 0xfd2fffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fd300000 size: 5300000 align: 26 gran: 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:18.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 01:01.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 01:01.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 01:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 01:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:1300000 align:24 gran:20 limit:febfffff
Assigned: PCI: 01:03.0 20 * [0xfc000000 - 0xfd0fffff] mem
Assigned: PCI: 01:01.0 20 * [0xfd100000 - 0xfd1fffff] mem
Assigned: PCI: 01:01.1 10 * [0xfd200000 - 0xfd200fff] mem
Assigned: PCI: 01:02.1 10 * [0xfd201000 - 0xfd201fff] mem
PCI: 00:18.0 allocate_resources_mem: next_base: fd202000 size: 1300000 align: 24 gran: 20 done
PCI: 01:01.0 allocate_resources_mem: base:fd100000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 02:09.0 10 * [0xfd100000 - 0xfd10ffff] mem
Assigned: PCI: 02:09.0 18 * [0xfd110000 - 0xfd11ffff] mem
Assigned: PCI: 02:09.0 30 * [0xfd120000 - 0xfd12ffff] mem
Assigned: PCI: 02:09.1 10 * [0xfd130000 - 0xfd13ffff] mem
Assigned: PCI: 02:09.1 18 * [0xfd140000 - 0xfd14ffff] mem
Assigned: PCI: 02:09.1 30 * [0xfd150000 - 0xfd15ffff] mem
PCI: 01:01.0 allocate_resources_mem: next_base: fd160000 size: 100000 align: 20 gran: 20 done
PCI: 01:03.0 allocate_resources_mem: base:fc000000 size:1100000 align:24 gran:20 limit:febfffff
Assigned: PCI: 04:06.0 10 * [0xfc000000 - 0xfcffffff] mem
Assigned: PCI: 04:05.0 30 * [0xfd000000 - 0xfd07ffff] mem
Assigned: PCI: 04:06.0 30 * [0xfd080000 - 0xfd09ffff] mem
Assigned: PCI: 04:08.0 18 * [0xfd0a0000 - 0xfd0bffff] mem
Assigned: PCI: 04:00.0 10 * [0xfd0c0000 - 0xfd0c0fff] mem
Assigned: PCI: 04:00.1 10 * [0xfd0c1000 - 0xfd0c1fff] mem
Assigned: PCI: 04:06.0 18 * [0xfd0c2000 - 0xfd0c2fff] mem
Assigned: PCI: 04:08.0 10 * [0xfd0c3000 - 0xfd0c3fff] mem
Assigned: PCI: 04:05.0 24 * [0xfd0c4000 - 0xfd0c43ff] mem
PCI: 01:03.0 allocate_resources_mem: next_base: fd0c4400 size: 1100000 align: 24 gran: 20 done
Root Device assign_resources, bus 0 link: 0
split: 128K table at =f7fe0000
0: mmio_basek=003e0000, basek=003e0000, limitk=00400000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fd2fffff] size 0x01300000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 1 link: 0
PCI: 01:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 01:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 01:01.0 20 <- [0x00fd100000 - 0x00fd1fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 01:01.0 assign_resources, bus 2 link: 0
PCI: 02:09.0 10 <- [0x00fd100000 - 0x00fd10ffff] size 0x00010000 gran 0x10 mem64
PCI: 02:09.0 18 <- [0x00fd110000 - 0x00fd11ffff] size 0x00010000 gran 0x10 mem64
PCI: 02:09.0 30 <- [0x00fd120000 - 0x00fd12ffff] size 0x00010000 gran 0x10 romem
PCI: 02:09.1 10 <- [0x00fd130000 - 0x00fd13ffff] size 0x00010000 gran 0x10 mem64
PCI: 02:09.1 18 <- [0x00fd140000 - 0x00fd14ffff] size 0x00010000 gran 0x10 mem64
PCI: 02:09.1 30 <- [0x00fd150000 - 0x00fd15ffff] size 0x00010000 gran 0x10 romem
PCI: 01:01.0 assign_resources, bus 2 link: 0
PCI: 01:01.1 10 <- [0x00fd200000 - 0x00fd200fff] size 0x00001000 gran 0x0c mem64
PCI: 01:02.1 10 <- [0x00fd201000 - 0x00fd201fff] size 0x00001000 gran 0x0c mem64
PCI: 01:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 01:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 01:03.0 20 <- [0x00fc000000 - 0x00fd0fffff] size 0x01100000 gran 0x14 bus 04 mem
PCI: 01:03.0 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00fd0c0000 - 0x00fd0c0fff] size 0x00001000 gran 0x0c mem
PCI: 04:00.1 10 <- [0x00fd0c1000 - 0x00fd0c1fff] size 0x00001000 gran 0x0c mem
PCI: 04:05.0 10 <- [0x0000001450 - 0x0000001457] size 0x00000008 gran 0x03 io
PCI: 04:05.0 14 <- [0x0000001460 - 0x0000001463] size 0x00000004 gran 0x02 io
PCI: 04:05.0 18 <- [0x0000001458 - 0x000000145f] size 0x00000008 gran 0x03 io
PCI: 04:05.0 1c <- [0x0000001464 - 0x0000001467] size 0x00000004 gran 0x02 io
PCI: 04:05.0 20 <- [0x0000001440 - 0x000000144f] size 0x00000010 gran 0x04 io
PCI: 04:05.0 24 <- [0x00fd0c4000 - 0x00fd0c43ff] size 0x00000400 gran 0x0a mem
PCI: 04:05.0 30 <- [0x00fd000000 - 0x00fd07ffff] size 0x00080000 gran 0x13 romem
PCI: 04:06.0 10 <- [0x00fc000000 - 0x00fcffffff] size 0x01000000 gran 0x18 mem
PCI: 04:06.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 04:06.0 18 <- [0x00fd0c2000 - 0x00fd0c2fff] size 0x00001000 gran 0x0c mem
PCI: 04:06.0 30 <- [0x00fd080000 - 0x00fd09ffff] size 0x00020000 gran 0x11 romem
PCI: 04:08.0 10 <- [0x00fd0c3000 - 0x00fd0c3fff] size 0x00001000 gran 0x0c mem
PCI: 04:08.0 14 <- [0x0000001400 - 0x000000143f] size 0x00000040 gran 0x06 io
PCI: 04:08.0 18 <- [0x00fd0a0000 - 0x00fd0bffff] size 0x00020000 gran 0x11 mem
PCI: 01:03.0 assign_resources, bus 4 link: 0
PCI: 01:04.0 assign_resources, bus 0 link: 0
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io
PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
PCI: 01:04.0 assign_resources, bus 0 link: 0
PCI: 01:04.1 20 <- [0x0000002420 - 0x000000242f] size 0x00000010 gran 0x04 io
PCI: 01:04.2 10 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io
PCI: 01:04.3 58 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:18.0 assign_resources, bus 1 link: 0
PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base f8000000 size 5300000 align 26 gran 0 limit febfffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
PCI_DOMAIN: 0000 resource base c0000 size f7f40000 align 0 gran 0 limit 0 flags e0004200 index 20
PCI: 00:18.0 child on link 0 PCI: 01:01.0
PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff flags 60080100 index 1c0
PCI: 00:18.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 40081200 index 2
PCI: 00:18.0 resource base fc000000 size 1300000 align 24 gran 20 limit febfffff flags 60080200 index 1b8
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1b0
PCI: 01:01.0 child on link 0 PCI: 02:06.0
PCI: 01:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 01:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
PCI: 01:01.0 resource base fd100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
PCI: 02:06.0
PCI: 02:06.1
PCI: 02:09.0
PCI: 02:09.0 resource base fd100000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 10
PCI: 02:09.0 resource base fd110000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 18
PCI: 02:09.0 resource base fd120000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
PCI: 02:09.1
PCI: 02:09.1 resource base fd130000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 10
PCI: 02:09.1 resource base fd140000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 18
PCI: 02:09.1 resource base fd150000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
PCI: 01:01.1
PCI: 01:01.1 resource base fd200000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 10
PCI: 01:02.0
PCI: 01:02.1
PCI: 01:02.1 resource base fd201000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 10
PCI: 01:03.0 child on link 0 PCI: 04:00.0
PCI: 01:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 01:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
PCI: 01:03.0 resource base fc000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base fd0c0000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
PCI: 04:00.1
PCI: 04:00.1 resource base fd0c1000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
PCI: 04:00.2
PCI: 04:01.0
PCI: 04:05.0
PCI: 04:05.0 resource base 1450 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
PCI: 04:05.0 resource base 1460 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
PCI: 04:05.0 resource base 1458 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
PCI: 04:05.0 resource base 1464 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
PCI: 04:05.0 resource base 1440 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 04:05.0 resource base fd0c4000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24
PCI: 04:05.0 resource base fd000000 size 80000 align 19 gran 19 limit febfffff flags 60002200 index 30
PCI: 04:06.0
PCI: 04:06.0 resource base fc000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10
PCI: 04:06.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
PCI: 04:06.0 resource base fd0c2000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 18
PCI: 04:06.0 resource base fd080000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
PCI: 04:08.0
PCI: 04:08.0 resource base fd0c3000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
PCI: 04:08.0 resource base 1400 size 40 align 6 gran 6 limit ffff flags 60000100 index 14
PCI: 04:08.0 resource base fd0a0000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 18
PCI: 01:04.0 child on link 0 PNP: 002e.0
PCI: 01:04.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 01:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 01:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 002e.6
PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.7
PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.8
PNP: 002e.9
PNP: 002e.a
PNP: 002e.b
PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PCI: 01:04.1
PCI: 01:04.1 resource base 2420 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 01:04.2
PCI: 01:04.2 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000100 index 10
PCI: 01:04.3
PCI: 01:04.3 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 58
PCI: 01:04.5
PCI: 01:04.6
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94
Done allocating resources.
POST: 0x88
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 10f1/2882
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 10f1/2882
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 01:01.0 bridge ctrl <- 0003
PCI: 01:01.0 cmd <- 06
PCI: 01:01.1 subsystem <- 10f1/2882
PCI: 01:01.1 cmd <- 06
PCI: 01:02.1 subsystem <- 10f1/2882
PCI: 01:02.1 cmd <- 06
PCI: 01:03.0 bridge ctrl <- 000b
PCI: 01:03.0 cmd <- 07
PCI: 01:04.0 subsystem <- 10f1/2882
PCI: 01:04.0 cmd <- 0f
PCI: 01:04.1 subsystem <- 10f1/2882
PCI: 01:04.1 cmd <- 01
PCI: 01:04.2 subsystem <- 10f1/2882
PCI: 01:04.2 cmd <- 01
PCI: 01:04.3 subsystem <- 10f1/2882
PCI: 01:04.3 cmd <- 01
PCI: 02:09.0 subsystem <- 10f1/2882
PCI: 02:09.0 cmd <- 02
PCI: 02:09.1 subsystem <- 10f1/2882
PCI: 02:09.1 cmd <- 02
PCI: 04:00.0 subsystem <- 10f1/2882
PCI: 04:00.0 cmd <- 02
PCI: 04:00.1 subsystem <- 10f1/2882
PCI: 04:00.1 cmd <- 02
PCI: 04:05.0 cmd <- 03
PCI: 04:06.0 subsystem <- 10f1/2882
PCI: 04:06.0 cmd <- 83
PCI: 04:08.0 subsystem <- 10f1/2882
PCI: 04:08.0 cmd <- 03
W83627HF HWM SMBus enabled
done.
POST: 0x89
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor AMD device f5a
CPU: family 0f, model 05, stepping 0a
POST: 0x60
Enabling cache
CPU ID 0x80000001: f5a
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
Setting variable MTRR 2, base: 3072MB, range: 512MB, type WB
Setting variable MTRR 3, base: 3584MB, range: 256MB, type WB
Setting variable MTRR 4, base: 3840MB, range: 128MB, type WB
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
POST: 0x6a
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93
microcode: equivalent rev id = 0x004a, current patch id = 0x00000000
microcode: patch id to apply = 0x00000047
microcode: updated to patch id = 0x00000047 success
CPU model AMD Opteron(tm) Processor 242
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
Scrubbing Disabled
Clearing memory 2048K - 4194304K: --------------------------------------------------------------- done
CPU #0 initialized
All AP CPUs stopped (0 loops)
PCI: 00:18.0 init
PCI: 00:18.1 init
PCI: 00:18.2 init
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 01:01.0 init
PCI: 01:03.0 init
PCI: 01:04.0 init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
RTC Init
enabling HPET @0xfed00000
PCI: 01:04.1 init
IDE1 IDE0 PCI: 01:04.3 init
set power off after power fail
PCI: 02:09.0 init
PCI: 02:09.1 init
PCI: 04:05.0 init
SIL3114 set to IDE compatible mode
PCI: 04:06.0 init
PCI: 04:08.0 init
PNP: 002e.0 init
PNP: 002e.2 init
PNP: 002e.5 init
Keyboard init...
No PS/2 keyboard detected.
PNP: 002e.b init
base = 0x0295, reg = 0x40, value = 0x81
base = 0x0295, reg = 0x48, value = 0x2a
base = 0x0295, reg = 0x4a, value = 0x21
base = 0x0295, reg = 0x4e, value = 0x80
base = 0x0295, reg = 0x43, value = 0xff
base = 0x0295, reg = 0x44, value = 0x3f
base = 0x0295, reg = 0x4c, value = 0x18
base = 0x0295, reg = 0x4d, value = 0x95
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 01:01.0: enabled 1
PCI: 02:06.0: enabled 0
PCI: 02:06.1: enabled 0
PCI: 02:09.0: enabled 1
PCI: 02:09.1: enabled 1
PCI: 01:01.1: enabled 1
PCI: 01:02.0: enabled 0
PCI: 01:02.1: enabled 1
PCI: 01:03.0: enabled 1
PCI: 04:00.0: enabled 1
PCI: 04:00.1: enabled 1
PCI: 04:00.2: enabled 0
PCI: 04:01.0: enabled 0
PCI: 04:05.0: enabled 1
PCI: 04:06.0: enabled 1
PCI: 04:08.0: enabled 1
PCI: 01:04.0: enabled 1
PNP: 002e.0: enabled 1
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PCI: 01:04.1: enabled 1
PCI: 01:04.2: enabled 1
PCI: 01:04.3: enabled 1
PCI: 01:04.5: enabled 0
PCI: 01:04.6: enabled 0
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
POST: 0x8a
Re-Initializing CBMEM area to 0xf7fe0000
Initializing CBMEM area to 0xf7fe0000 (131072 bytes)
Adding CBMEM entry as no. 1
Moving GDT to f7fe0200...ok
High Tables Base is f7fe0000.
POST: 0x9a
Writing IRQ routing tables to 0xf0000...
setting Onboard AMD Southbridge
Assigning IRQ 10 to 1:4.2
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x400
setting Onboard AMD USB
Assigning IRQ 10 to 4:0.0
i8259_configure_irq_trigger: current interrupts are 0x400
i8259_configure_irq_trigger: try to set interrupts 0x400
Assigning IRQ 10 to 4:0.1
i8259_configure_irq_trigger: current interrupts are 0x400
i8259_configure_irq_trigger: try to set interrupts 0x400
Assigning IRQ 10 to 4:0.2
i8259_configure_irq_trigger: current interrupts are 0x400
i8259_configure_irq_trigger: try to set interrupts 0x400
setting Onboard ATI Display Adapter
Assigning IRQ 11 to 4:6.0
i8259_configure_irq_trigger: current interrupts are 0x400
i8259_configure_irq_trigger: try to set interrupts 0xc00
setting Slot 1
setting Slot 2
setting Slot 3
setting Slot 4
setting Slot 5
setting Onboard SI Serial ATA
Assigning IRQ 10 to 4:5.0
i8259_configure_irq_trigger: current interrupts are 0xc00
i8259_configure_irq_trigger: try to set interrupts 0xc00
setting Onboard Intel NIC
Assigning IRQ 11 to 4:8.0
i8259_configure_irq_trigger: current interrupts are 0xc00
i8259_configure_irq_trigger: try to set interrupts 0xc00
setting Onboard Adaptec SCSI
setting Onboard Broadcom NIC
Assigning IRQ 5 to 2:9.0
i8259_configure_irq_trigger: current interrupts are 0xc00
i8259_configure_irq_trigger: try to set interrupts 0xc20
Assigning IRQ 9 to 2:9.1
i8259_configure_irq_trigger: current interrupts are 0xc20
i8259_configure_irq_trigger: try to set interrupts 0xe20
done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0xf7fe0400...
setting Onboard AMD Southbridge
Assigning IRQ 10 to 1:4.2
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
setting Onboard AMD USB
Assigning IRQ 10 to 4:0.0
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
Assigning IRQ 10 to 4:0.1
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
Assigning IRQ 10 to 4:0.2
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
setting Onboard ATI Display Adapter
Assigning IRQ 11 to 4:6.0
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
setting Slot 1
setting Slot 2
setting Slot 3
setting Slot 4
setting Slot 5
setting Onboard SI Serial ATA
Assigning IRQ 10 to 4:5.0
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
setting Onboard Intel NIC
Assigning IRQ 11 to 4:8.0
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
setting Onboard Adaptec SCSI
setting Onboard Broadcom NIC
Assigning IRQ 5 to 2:9.0
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
Assigning IRQ 9 to 2:9.1
i8259_configure_irq_trigger: current interrupts are 0xe20
i8259_configure_irq_trigger: try to set interrupts 0xe20
done.
PIRQ table: 224 bytes.
POST: 0x9b
Wrote the mp table end at: 000f0410 - 000f0608
Adding CBMEM entry as no. 3
Wrote the mp table end at: f7fe1410 - f7fe1608
MP table: 520 bytes.
Adding CBMEM entry as no. 4
smbios_write_tables: f7fe2400
Root Device (Tyan S2882)
APIC_CLUSTER: 0 (AMD K8 Root Complex)
APIC: 00 (Socket 940 CPU)
PCI_DOMAIN: 0000 (AMD K8 Root Complex)
PCI: 00:18.0 (AMD K8 Northbridge)
PCI: 01:01.0 (unknown)
PCI: 02:06.0 (unknown)
PCI: 02:06.1 (unknown)
PCI: 02:09.0 (unknown)
PCI: 02:09.1 (unknown)
PCI: 01:01.1 (unknown)
PCI: 01:02.0 (unknown)
PCI: 01:02.1 (unknown)
PCI: 01:03.0 (AMD-8111 Southbridge)
PCI: 04:00.0 (AMD-8111 Southbridge)
PCI: 04:00.1 (AMD-8111 Southbridge)
PCI: 04:00.2 (AMD-8111 Southbridge)
PCI: 04:01.0 (AMD-8111 Southbridge)
PCI: 04:05.0 (AMD-8111 Southbridge)
PCI: 04:06.0 (AMD-8111 Southbridge)
PCI: 04:08.0 (AMD-8111 Southbridge)
PCI: 01:04.0 (AMD-8111 Southbridge)
PNP: 002e.0 (Winbond W83627HF Super I/O)
PNP: 002e.1 (Winbond W83627HF Super I/O)
PNP: 002e.2 (Winbond W83627HF Super I/O)
PNP: 002e.3 (Winbond W83627HF Super I/O)
PNP: 002e.5 (Winbond W83627HF Super I/O)
PNP: 002e.6 (Winbond W83627HF Super I/O)
PNP: 002e.7 (Winbond W83627HF Super I/O)
PNP: 002e.8 (Winbond W83627HF Super I/O)
PNP: 002e.9 (Winbond W83627HF Super I/O)
PNP: 002e.a (Winbond W83627HF Super I/O)
PNP: 002e.b (Winbond W83627HF Super I/O)
PCI: 01:04.1 (AMD-8111 Southbridge)
PCI: 01:04.2 (AMD-8111 Southbridge)
PCI: 01:04.3 (AMD-8111 Southbridge)
PCI: 01:04.5 (AMD-8111 Southbridge)
PCI: 01:04.6 (AMD-8111 Southbridge)
PCI: 00:18.1 (AMD K8 Northbridge)
PCI: 00:18.2 (AMD K8 Northbridge)
PCI: 00:18.3 (AMD K8 Northbridge)
SMBIOS tables: 280 bytes.
POST: 0x9d
Adding CBMEM entry as no. 5
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum dbdf
New low_table_end: 0x00000528
Now going to write high coreboot table at 0xf7fe2c00
rom_table_end = 0xf7fe2c00
Adjust low_table_end from 0x00000528 to 0x00001000
Adjust rom_table_end from 0xf7fe2c00 to 0xf7ff0000
Adding high table area
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-00000000f7fdffff: RAM
3. 00000000f7fe0000-00000000f7ffffff: CONFIGURATION TABLES
Wrote coreboot table at: f7fe2c00, 0x1cc bytes, checksum f670
coreboot table: 484 bytes.
POST: 0x9e
POST: 0x9d
Multiboot Information structure has been written.
0. FREE SPACE f7feac00 00015400
1. GDT f7fe0200 00000200
2. IRQ TABLE f7fe0400 00001000
3. SMP TABLE f7fe1400 00001000
4. SMBIOS f7fe2400 00000800
5. COREBOOT f7fe2c00 00008000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Loading segment from rom address 0xfff959b8
code (compression=1)
New segment dstaddr 0xe79a0 memsize 0x18660 srcaddr 0xfff959f0 filesize 0xc578
(cleaned up) New segment addr 0xe79a0 size 0x18660 offset 0xfff959f0 filesize 0xc578
Loading segment from rom address 0xfff959d4
Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e79a0 memsz: 0x0000000000018660 filesz: 0x000000000000c578
lb: [0x0000000000100000, 0x0000000000145000)
Post relocation: addr: 0x00000000000e79a0 memsz: 0x0000000000018660 filesz: 0x000000000000c578
using LZMA
[ 0x000e79a0, 00100000, 0x00100000) <- fff959f0
dest 000e79a0, end 00100000, bouncebuffer f7f56000
Loaded segments
Jumping to boot code at fc7e0
POST: 0xf8
CPU0: stack: 00140000 - 00141000, lowest used address 001409e8, stack used: 1560 bytes
entry = 0x000fc7e0
lb_start = 0x00100000
lb_size = 0x00045000
adjust = 0xf7e9b000
buffer = 0xf7f56000
elf_boot_notes = 0x00121080
adjusted_boot_notes = 0xf7fbc080
Start bios (version rel-1.7.1-0-g51755c3-20121205_211827-rukbat)
Found mainboard Tyan S2882
Ram Size=0xf7fe0000 (0x0000000000000000 high)
Relocating low data from 0x000e81e0 to 0x000ef790 (size 2153)
Relocating init from 0x000e8a49 to 0xf7fc68e0 (size 38387)
Found CBFS header at 0xfffff8a8
CPU Mhz=1594
Found 4 PCI devices (max PCI bus is 00)
Found 1 cpu(s) max supported 1 cpu(s)
Copying PIR from 0xf7fe0400 to 0x000fdb10
Copying MPTABLE from 0xf7fe1400/f7fe1410 to 0x000fd900
Copying SMBIOS entry point from 0xf7fe2400 to 0x000fd8e0
Scan for VGA option rom
Found 0 lpt ports
Found 1 serial ports
Got ps2 nak (status=51)
All threads complete.
Scan for option roms
Press F12 for boot menu.
Space available for UMB: 000c0000-000ef000
Returned 65536 bytes of ZoneHigh
e820 map has 5 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 00000000f7fe0000 = 1 RAM
4: 00000000f7fe0000 - 00000000f8000000 = 2 RESERVED
enter handle_19:
NULL
Booting from Floppy...
Boot failed: could not read the boot disk
enter handle_18:
NULL
Booting from Hard Disk...
Boot failed: could not read the boot disk
enter handle_18:
NULL
No bootable device. Retrying in 60 seconds.
Rebooting.
In resume (status=0)
In 32bit resume
Attempting a hard reboot
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